Floating point unit power reduction scheme
View Patent ↗A system and method for reducing the power consumption of a floating point unit of a processor wherein the processor iteratively performs floating point calculations based upon one or more input operands. The exponential value of a floating point is precalculated within an iterative loop through a superscalar instruction buffer resident on the processor that holds at least 3 iterations of the largest single cycle iteration possible on the processor, and the precalculated exponent value is used to generate a bit mask that enables a minimal number of fractional data flow bits. Alternately, a look-ahead can be used to obtain the exponent value from at least two subsequent iterations of the loop.
1. A system for reducing the power consumption of a floating point unit of a processor, comprising:
a processor that selectively and iteratively performs floating point calculations based upon one or more input operands;
a floating point multiply adder resident in the floating point unit, the floating point multiply adder comprised of a multiply array and an adder, and including at least a partial bit mask; and
wherein upon at least a first iteration of a floating point calculation, the floating point multiply adder assuming the exponent value based upon the one or more input operands, and successive iterations of floating point calculations utilize the assumed exponent value.
2. The system of claim 1 , wherein, upon determining that the assumption of exponent value based upon the propagated exponent value is incorrect, the floating point unit stalling the propagation of the incorrect exponent values and receiving the correct exponent value.
3. The system of claim 1 , wherein the partial bit mask of the floating point multiply adder propagates ½ of the multiply array bits and ⅓ of the adder bits.
4. The system of claim 1 , wherein the exponential value of one of the source operands is propagated in each successive iteration of the floating point calculations.
5. A system for reducing the power consumption of a floating point unit of a processor, comprising:
a processor that selectively and iteratively performs floating point calculations based upon one or more input operands;
a superscalar instruction buffer resident on the processor, the instruction buffer holding instructions and floating point calculations, and at least sufficiently large to hold 3 iterations of the largest single cycle iteration possible on the processor; and
a floating point look ahead selector resident in the floating point unit, the floating point look ahead selector selecting the exponent value from a subsequent iteration within the instruction buffer; and
wherein successive iterations of floating point calculations assume exponent value based upon the selected exponent value of the look-ahead selector.
6. The system of claim 5 , wherein the instruction buffer pipelines two iterations of floating point calculations before selecting the exponent value.
7. The system of claim 5 , wherein floating point look ahead selector prefetches the stored instructions in the instruction buffer from two previous iterations.
8. The system of claim 5 , wherein the instruction buffer holds at least 16 instructions.
9. A method for reducing the power consumption of a floating point unit of a processor that selectively and iteratively performs floating point calculations based upon one or more input operands, the method comprising the steps of:
performing a first iteration of a loop wherein a floating point calculation is made in the floating point unit based upon one or more input operands;
assuming the exponent value based upon the one or more input operands, and performing at least a second iteration of the loop and making a floating point calculation assuming exponent value based upon the assumed exponent values.
10. The method of claim 9 , further including the steps of:
determining if the assumption of exponent value is incorrect; and
if the assumed exponent value is incorrect, placing the correct exponent value into at least the second iteration of the loop prior to making a floating point calculation.
11. The method of claim 9 , wherein the step of assuming the exponent value based upon the one or more input operands is assuming the exponent value with a floating point multiply adder in the first iteration.
12. The method of claim 9 , wherein the step of assuming the exponential value based upon the one or more input operands is assuming the exponent value with a look-ahead selector and a superscalar instruction buffer resident on the processor, the instruction buffer holding instructions and floating point calculations, and at least sufficiently large to hold 3 iterations of the largest single cycle iteration possible on the processor, and the look-ahead selector obtaining the exponent value from a subsequent iteration of the loop.
13. The method of claim 12 , further comprising the step of performing a second iteration of a loop wherein a floating point calculation is made in the floating point unit based upon one or more input operands, the look-ahead selection obtaining the exponent value from a second subsequent iteration of the loop.