Apparatus and method for a hash processing system using integrated message digest and secure hash architectures
View Patent ↗A hash processing system and method for reducing the number of clock cycles required to implement the SHA1 and MD5 hash algorithms by using a common hash memory having multiple storage areas each coupled to one of two or more hash channels. The system further provides implicit padding on-the-fly as data is read from the common hash memory. The system shares register and other circuit resources for MD5 and SHA1 hash circuits that are implemented in each hash channel, and uses pipelined, two-channel SHA1 and pipelined, single-channel MD5 hash architectures to reduce the effective time required to implement the SHA1 and MD5 algorithms.
1. A hash circuit comprising:
a hash memory for receiving input data, wherein the hash memory is accessed using a plurality of address locations;
a hash channel, coupled to receive the input data from the hash memory, to hash the input data using a hash algorithm, wherein the hash channel is adapted to implement the hash algorithm in first and second rounds operating substantially in parallel; and wherein:
the hash circuit performs a first read access of the hash memory to provide a first data unit for processing in the first round of the hash algorithm and a second read access of the hash memory to provide a second data unit for processing in the second round of the hash algorithm;
the first read access further comprises reading and logically combining additional data units for processing in the first round of the hash algorithm; and
the second read access further comprises reading and logically combining additional data units for processing in the second round of the hash algorithm.
2. The hash circuit of claim 1 wherein the hash algorithm is a secure hash algorithm.
3. The hash circuit of claim 1 wherein the first data unit is a first 32-bit word and the second data unit is a second 32-bit word.
4. The hash circuit of claim 1 wherein:
the hash circuit reads the first data unit from only even address locations of the plurality of address locations; and
the hash circuit reads the second data unit from only odd address locations of the plurality of address locations.
5. The hash circuit of claim 1 wherein:
the logically combining of the additional data units from the first read access comprises the XOR'ing of a first set of 32-bit words; and
the logically combining of the additional data units from the second read access comprises the XOR'ing of a second set of 32-bit words.
6. A hash circuit comprising:
an adder adapted to implement the SHA1 algorithm, wherein the adder computes a first round and a second round of the SHA1 algorithm substantially in parallel, and implements a processing pipeline for each of the first and second rounds using an earlier clock cycle and a current clock cycle, the earlier clock cycle preceding the current clock cycle in time; and
a hash memory coupled to provide data to the adder for hash processing,
wherein for the first round, the adder is adapted to:
compute a Kt function value in the earlier clock cycle,
compute a non-linear function value in the earlier clock cycle,
receive a temporary variable he or hc input in the earlier clock cycle,
receive a read data input in the earlier clock cycle,
receive a shifted temporary variable ha input in the current clock cycle,
and
provide a temporary output; and
wherein for the second round, the adder is adapted to:
compute a Kt function value,
compute a non-linear function value,
receive a temporary variable hd or shifted temporary variable hb input,
receive a read data input, and
couple the temporary output from the first round to be an input to the second round.
7. The hash circuit of claim 2 wherein for the second round, the adder is adapted to:
compute the Kt function value in the earlier clock cycle;
receive the temporary variable hd or shifted temporary variable hb input in the earlier clock cycle;
receive the read data input in the earlier clock cycle;
compute the non-linear function value in the current clock cycle; and
couple the temporary output from the first round in the current clock cycle.
8. The hash circuit of claim 7 wherein the adder comprises:
a first register to latch, for the first round, a first sum corresponding to the Kt function value, the non-linear function value, the temporary variable he or hc input and the read data input.
a second register to latch, for the second round, a second stun corresponding to the Kt function value, the temporary variable lid or shifted temporary variable hb input, and the read data input.
9. A hash circuit comprising:
an adder adapted to implement the SHA1 algorithm, wherein the adder computes a first round and a second round of the SHA1 algorithm substantially in parallel; and
a hash memory coupled to provide data to the adder for bash processing,
wherein the adder, for processing in the first round, comprises:
a first carry save adder to receive a non-linear function value, a Kt function value, and a temporary variable he or hc input;
a second carry save adder coupled to receive a read data input from the hash memory and an output from the first carry save adder;
a third carry save adder to receive a shifted temporary variable ha input and coupled to receive an output of the second carry save adder, and
a first register coupled between the second and third carry save adders; and wherein the adder, for processing in the second round, further comprises;
a fourth carry save adder coupled to receive a Kt function value, a temporary variable hd or shifted temporary variable hb input, and a read data input;
a fifth carry save adder to receive a non-linear function value and coupled to receive an output of the fourth carry save adder;
a sixth carry save adder coupled to receive a temporary output from the first round and coupled to receive an output of the fifth carry save adder; and
a second register coupled between the fourth and fifth carry save adders.