Pipelined parallel processing of feedback loops in a digital circuit
Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected. A clocking rate (C) is selected for the digital circuit such that a product (P), P being equal to B times C, is equal to at least 1 gigabit per second. An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed. This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero. The initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream. An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines. The unfolded circuit is retimed to achieve the selected clocking rate (C).
1. A method, comprising:
selecting a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit;
selecting a clocking rate (C) for the digital circuit, wherein a product (P), P being equal to B times C, is equal to at least 1 gigabit per second;
forming an initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P, the initial circuit including a feedback loop having N+1 delays, wherein N is a whole number greater than zero;
unfolding the initial circuit by a factor of B to form B parallel processing pipelines for the bits of the bit-stream;
forming an N-step look-ahead network to provide inputs to the B parallel processing pipelines; and
retiming the unfolded, initial circuit to achieve the selected clocking rate (C).
2. The method of claim 1 , wherein said unfolding step comprises:
unfolding the initial circuit by a factor equal to the number of delays in the feedback loop.
3. The method of claim 1 , wherein said unfolding step comprises:
unfolding the initial circuit by a factor less than the number of delays in the feedback loop.
4. The method of claim 1 , wherein said unfolding step comprises:
unfolding the initial circuit by a factor greater than the number of delays in the feedback loop.
5. The method of claim 1 , wherein said step of forming the initial circuit comprises:
forming the initial circuit to have an innermost nested feedback loop, wherein the innermost nested feedback loop has N+1 delays.
6. The method of claim 5 , wherein said unfolding step comprises:
unfolding the initial circuit by a factor equal to the number of delays in the innermost nested feedback loop.
7. The method of claim 5 , wherein said unfolding step comprises:
unfolding the initial circuit by a factor less than the number of delays in the innermost nested feedback ioop.
8. The method of claim 5 , wherein said unfolding step comprises:
unfolding the initial circuit by a factor greater than the number of delays in the innermost nested feedback loop.
9. The method of claim 1 , wherein said step of forming the initial circuit comprises:
forming the initial circuit using a multiplexer loop.
10. The method of claim 1 , wherein said unfolding step comprises:
unfolding the initial circuit to form at least two parallel processing circuits.
11. The method of claim 1 , wherein said step of forming the N-step look-ahead network comprises:
forming an initial look-ahead network; and
unfolding the initial look-ahead network by the factor B.
12. A digital circuit, wherein the digital circuit is desianed by a method, the method comprising:
selecting a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit;
selecting a clocking rate (C) for the digital circuit, wherein a product (P), P being euual to B times C, is equal to at least 1 gigabit per second;
forming an initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P, the initial circuit including a feedback loop having N+1 delays, wherein N is a whole number greater than zero;
unfolding the initial circuit by a factor of B to form B parallel processing pipelines for the bits of the bit-stream;
forming an N-step look-ahead network to provide inputs to the B parallel processing pipelines; and
retiming the unfolded, initial circuit to achieve the selected clocking rate (C).
13. A decision feedback equalizer, comprising the digital circuit of claim 12 .
14. A transceiver, comprising the digital circuit of claim 12 .
15. A digital circuit that operates at a data processing rate in excess of 1 gigabit per second, comprising:
an N-level look-ahead network that converts a plurality of input values from a bit-stream to a plurality of intermediate values; and
at least two parallel processing pipelines electrically coupled to the N-level look-ahead network, the at least two parallel processing pipelines being formed by:
unfolding an initial circuit capable of serially processing the bits of the bit-stream, the initial circuit including a feedback loop having N+1 delays, wherein N is a whole number greater than zero; and
retiming the unfolded, initial circuit to achieve a selected clocking rate.
16. The digital circuit of claim 15 , wherein the initial circuit is unfolded by a factor less than the number of delays in the feedback loop.
17. The digital circuit of claim 15 , wherein the initial circuit is unfolded by a factor equal to the number of delays in the feedback loop.
18. The digital circuit of claim 15 , wherein the initial circuit is unfolded by a factor greater than the number of delays in the feedback loop.
19. The digital circuit of claim 15 , wherein the digital circuit forms part of a decision feedback equalizer.
20. The digital circuit of claim 15 , wherein the digital circuit forms part of a transceiver.
21. The digital circuit of claim 15 , wherein the N-level look-ahead network is formed by forming an initial look-ahead network and unfolding the initial look-ahead network.