IP Library Granted Patent US 7,229,005
Granted Patent B2
US 7,229,005 · App. 10/147,226 · Granted Jun 12, 2007

Display device having an improved video signal drive circuit

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Quick Facts
Patent No.
US 7,229,005
App. No.
10/147,226
Granted
Jun 12, 2007
Kind
B2
Abstract

A display device has a video circuit for pixels arranged in a matrix. The video circuit includes a digital data store section; a transfer-data processing section for generating a data signal at a time assigned to one of gray scale levels for the data in synchronism with a supplied clock; a gray-scale voltage generator for generating gray-scale voltages; a selection gate circuit for successively generating gate pulses associated with the gray-scale voltages, in synchronism with the clock; and a gray-scale voltage selector circuit for receiving the data signal via a selection-data transfer line provided for each of plural columns of the pixels, and for successively selecting the gray-scale voltages from the gray-scale voltage generator, in synchronism with the gate pulses. The gray-scale voltage selector circuit outputs as the video signal, one of the gray-scale voltages selected from the successively selected gray-scale voltages in synchronism with the data signal.

Claims (58)

1. A display device comprising:

a substrate;

a plurality of pixels arranged in a matrix array and formed on said substrate;

a selector circuit for selecting one from a plurality of rows of pixels in said matrix array; and

a video signal supplying circuit for supplying a video signal to each of pixels in said selected row in synchronism with said selection of said selected row, said video signal supplying circuit comprising:

a digital data store section for storing n-bit data information for each of said plurality of pixels, n being an integer equal to or greater than 3;

a transfer-data processing section for generating a data signal at a time assigned to one of a plurality of gray scale levels represented by said n-bit data information, in accordance with an output from said digital data store section, in synchronism with n kinds of clocks supplied to said transfer-data processing section, said n kinds being equal in number to the number of bits representing said n-bit data information, n being an integer equal to or greater than 3;

a gray-scale voltage generator for generating a plurality of gray scale voltages corresponding to said plurality of gray scale levels, respectively;

a selection gate circuit for successively generating a plurality of gate pulses associated with said plurality of gray-scale voltages, respectively, in synchronism with a fastest kind of said n kinds of clocks; and

a gray-scale voltage selector circuit section comprised of TFTs (Thin Film Transistors) formed on said substrate for receiving said data signal via one or more selection-data transfer lines smaller in number than 2 n formed on said substrate corresponding to each of a plurality of columns of pixels in said matrix array, and for successively selecting said plurality of gray-scale voltages generated by said gray-scale voltage generator, in synchronism with said gate pulses, n being an integer equal to or greater than 3,

wherein said gray-scale voltage selector circuit section outputs as said video signal, one of said plurality of gray-scale voltages selected from said successively selected gray-scale voltages in synchronism with said data signal.

2. A display device comprising:

a substrate;

a plurality of pixels arranged in a matrix array and formed on said substrate;

a selector circuit for selecting one from a plurality of rows of pixels in said matrix array; and

a video signal supplying circuit for supplying a video signal to each of pixels in said selected row in synchronism with said selection of said selected row, said video signal supplying circuit comprising:

a digital data store section for storing n-bit data information for each of said plurality of pixels, n being an integer equal to or greater than 3;

a transfer-data processing section for generating a data signal at a time assigned to one of a plurality of gray scale levels represented by said n-bit data information, in accordance with an output from said digital data store section, in synchronism with n kinds of clocks supplied to said transfer-data processing section, said n kinds being equal in number to the number of bits representing said n-bit data information, and n being an integer equal to or greater than 3;

a gray-scale voltage generator for generating a plurality of gray-scale voltages corresponding to said plurality of gray scale levels, respectively;

a selection gate circuit for successively generating a plurality of gate pulses associated with said plurality of gray-scale voltages, respectively, in synchronism with a fastest kind of said n kinds of clocks; and

a gray-scale voltage selector circuit section comprised of TFTs (Thin Film Transistors) formed on said substrate for receiving said data signal via one or more selection-data transfer lines smaller in number than 2 n , said one or more selection-data transfer lines being formed on said substrate corresponding to each of a plurality of columns of pixels in said matrix array, and for successively selecting said plurality of gray-scale voltages generated by said gray-scale voltage generator, in synchronism with said gate pulses, n being an integer equal to or greater than 3,

each of said plurality of selection-data transfer lines corresponding to one of a plurality of groups formed by dividing said plurality of gray-scale voltages,

wherein said gray-scale voltage selector circuit section outputs as said video signal, one of said plurality of gray-scale voltages selected from said successively selected gray-scale voltages in synchronism with said data signal.

3. A display device according to claim 2 , wherein said one or more selection-data transfer lines are smaller in number than said plurality of gray scale levels, and frequencies of said n kinds of clocks are successively lower or higher by a factor of 2.

4. A display device according to claim 1 , wherein said n kinds of clocks include at least said fastest kind and a kind having a frequency equal to that of said fastest kind divided by 2 (m−1) , where m is an integer from 2 to n, and n is an integer equal to or greater than 3.

5. A display device according to claim 1 , wherein said display device is a liquid crystal display device.

6. A display device according to claim 1 , wherein each of the plurality of pixels comprises a semiconductor layer which is formed of polysilicon.

7. A display device according to claim 6 , wherein said TFTs of the gray-scale voltage selector circuit section comprise a semiconductor layer which is formed of polysilicon disposed on the substrate.

8. A display device according to claim 7 , wherein the selection gate circuit comprises a semiconductor layer which is formed of polysilicon disposed on the substrate.

9. A display device according to claim 7 , wherein the transfer-data processing section comprises a semiconductor layer which is formed of polysilicon disposed on the substrate.

10. A display device according to claim 3 , wherein the display device is a liquid crystal display device.

11. A display device according to claim 3 , wherein each of the plurality of pixels is provided with a light-emitting element.

12. A display device according to claim 3 , wherein each of the plurality of pixels comprises a semiconductor layer which is formed of polysilicon.

13. A display device according to claim 12 , wherein the TFTs of the gray-scale voltage selector circuit section comprises a semiconductor layer which is formed of polysilicon disposed on the substrate.

14. A display device according to claim 13 , wherein the selection gate circuit comprises a semiconductor layer which is formed of polysilicon disposed on the substrate.

15. A display device according to claim 13 , wherein the transfer-data processing section comprises a semiconductor layer which is formed of polysilicon disposed on the substrate.

16. A display device comprising:

a substrate;

a plurality of pixels arranged in a matrix array and formed on said substrate;

a selector circuit for selecting one from a plurality of rows of pixels in said matrix array; and

a video signal supplying circuit for supplying a video signal to each of pixels in said selected row in synchronism with said selection of said selected row, said video signal supplying circuit comprising:

a digital data store section for storing n-bit data information for each of said plurality of pixels, n being an integer equal to or greater than 3;

a transfer-data processing section for generating a data signal at a time assigned to one of a plurality of gray scale levels represented by said n-bit data information, in accordance with an output from said digital data store section, in synchronism with n kinds of clocks supplied to said transfer-data processing section, said n kinds being equal in number to the number of bits representing said n-bit data information, n being an integer equal to or greater than 3;

a gray-scale voltage generator for generating a plurality of gray scale voltages corresponding to said plurality of gray scale levels, respectively;

a selection gate circuit for successively generating a plurality of gate pulses associated with said plurality of gray-scale voltages, respectively, in synchronism with a fastest kind of said n kinds of clocks; and

a gray-scale voltage selector circuit section comprised of TFTs (Thin Film Transistors) formed on said substrate for receiving said data signal via only a singular selection-data transfer line formed on said substrate corresponding to each of a plurality of columns of pixels in said matrix array, and for successively selecting said plurality of gray-scale voltages generated by said gray-scale voltage generator, in synchronism with said gate pulses,

wherein said gray-scale voltage selector circuit section outputs as said video signal, one of said plurality of gray-scale voltages selected from said successively selected gray-scale voltages in synchronism with said data signal.

17. A display device comprising:

a substrate;

a plurality of pixels arranged in a matrix array and formed on said substrate;

a selector circuit for selecting one from a plurality of rows of pixels in said matrix array; and

a video signal supplying circuit for supplying a video signal to each of pixels in said selected row in synchronism with said selection of said selected row, said video signal supplying circuit comprising:

a digital data store section for storing n-bit data information for each of said plurality of pixels, n being an integer equal to or greater than 3;

a transfer-data processing section for generating a data signal at a time assigned to one of a plurality of gray scale levels represented by said n-bit data information, in accordance with an output from said digital data store section, in synchronism with clocks supplied to said transfer-data processing section;

a gray-scale voltage generator for generating a plurality of gray scale voltages corresponding to said plurality of gray scale levels, respectively;

a selection gate circuit for successively generating a plurality of gate pulses associated with said plurality of gray-scale voltages, respectively, in synchronism with a fastest kind of said clocks; and

a gray-scale voltage selector circuit section comprised of TFTs (Thin Film Transistors) formed on said substrate for receiving said data signal via one or more selection-data transfer lines smaller in number than 2 n formed on said substrate corresponding to each of a plurality of columns of pixels in said matrix array, and for successively selecting said plurality of gray-scale voltages generated by said gray-scale voltage generator, in synchronism with said gate pulses, n being an integer equal to or greater than 3,

wherein said gray-scale voltage selector circuit section outputs as said video signal, one of said plurality of gray-scale voltages selected from said successively selected gray-scale voltages in synchronism with said data signal.

Assignments (4)
COMPANY SPLIT PLAN TRANSFERRING FIFTY (50) PERCENT SHARE OF PATENTS AND PATENT APPLICATIONS Recorded Dec 12, 2011
From: HITACHI DISPLAYS, LTD.
To: IPS ALPHA SUPPORT CO., LTD.
Reel/Frame 027362/0466 →
COMPANY SPLIT PLAN TRANSFERRING ONE HUNDRED (100) PERCENT SHARE OF PATENT AND PATENT APPLICATIONS Recorded Dec 12, 2011
From: HITACHI, LTD.
To: HITACHI DISPLAYS, LTD.
Reel/Frame 027362/0612 →
MERGER/CHANGE OF NAME Recorded Dec 12, 2011
From: IPS ALPHA SUPPORT CO., LTD.
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 027363/0315 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2002
From: MIYAZAWA, TOSHIO
To: HITACHI, LTD.
Reel/Frame 012914/0517 →