Liquid crystal display, thin film transistor array panel for liquid crystal display and manufacturing method thereof
View Patent ↗A gate wire is formed on the insulating substrate. The gate wire has gate lines, first and second gate electrodes connected to the gate lines, and gate pads. A gate insulating layer, first and second semiconductor layers and an ohmic contact layer are sequentially formed thereon. A data wire is formed on the ohmic contact layer. The data wire has first and second data lines, data line connectors, first and second source electrodes, first and second drain electrodes, and data pads. A passivation layer is formed on the data wire, and has contact holes respectively exposing the first and the second drain electrodes, and the gate and the data pads. Pixel electrodes, and subsidiary gate and data pads are formed on the passivation layer. As described above, the data line is provided at opposite sides of the pixel area so that variation in the pixel voltage due to the parasitic capacitance between the partitioned areas with different degree of misalignment is reduced. In addition, two TFTs are provided in each pixel area so that the parasitic capacitance between the gate and the drain electrodes in two respective partitioned areas with left-biased and right-biased misalignment is kept to be constant. In this way, the pixel voltage variation between the two partitioned areas is reduced to prevent non-uniformity in the brightness.
1. A thin film transistor (“TFT”) array panel for a liquid crystal display (“LCD”) comprising:
a gate wire formed on an insulating substrate, the gate wire including gate lines, and first and second gate electrodes connected to the gate lines and spaced apart from each other by a predetermined distance;
a gate insulating layer covering the gate wire;
first and second semiconductor layers formed on the gate insulating layer opposite the first and the second gate electrodes, respectively;
a data wire including first and second data lines intersecting the gate lines to define pixel areas and spaced apart tram each other by a predetermined distance, first and second source electrodes which are respective parts of the first and the second data lines, and first and second drain electrodes respectively facing the first and the second source electrodes;
a passivation layer with first and second contact holes respectively exposing the first and the second drain electrodes; and
a pixel electrode connected to the first and the second drain electrodes,
wherein the pixel electrode overlaps the first and the second data lines to cover an entire width of the first and the second data lines.
2. The TFT array panel of claim 1 wherein the first and the second data lines are applied with the same signal.
3. The TFT array panel of claim 1 wherein the data wire further includes data line connectors, respectively formed at the upper and the lower half parts of the pixel area, to interconnect the first and the second data lines.
4. The TFT array panel of claim 1 wherein the first and the second semiconductor layers and the data wire have the same planar shape except for areas between the first source electrode and the first drain electrode and between the second source electrode and the second drain electrode.
5. The TFT array panel of claim 1 further comprising ohmic contact layers formed between the first and second semiconductor layers and the data wire.
6. The TFT array panel of claim 5 wherein the ohmic contact layers and the data wire have the same planar shape.
7. The TFT array panel of claim 1 wherein the gate wire further includes gate pads for applying signals to the gate lines, the data wire further has data pads for applying signals to the data lines, and the passivation layer further has third and fourth contact holes respectively exposing the gate and the data pads, and wherein the TFT array panel further comprises subsidiary gate and data pads formed of the same layer as the pixel electrode and connected to the gate and the data pads through the third and the fourth contact holes, respectively.
8. A liquid crystal display (“LCD”) comprising:
a first insulating substrate;
a gate wire formed on the first insulating substrate, the gate wire including gate lines, and first and second gate electrodes connected to the gate lines and spaced apart from each other by a predetermined distance;
a gate insulating layer covering the gate wire;
first and second semiconductor layers formed on the gate insulating layer opposite the first and the second gate electrodes, respectively;
a data wire including first and second data lines intersecting the gate lines to define pixel areas and spaced apart from each other by a predetermined distance, first and second source electrodes which are respective parts of the first and the second data lines, and first and second drain electrodes respectively facing the first and the second source electrodes;
a passivation layer with first and second contact holes respectively exposing the first and the second drain electrodes;
a pixel electrode connected to the first and the second drain electrodes;
a first domain partitioning member formed on the first insulating substrate;
a second insulating substrate opposite the first insulating substrate;
a color filter formed on the second insulating substrate;
a common electrode formed on the color filter; and
a second domain partitioning member formed on the second insulating substrates
wherein the pixel electrode overlaps the data wire having the first and the second data lines at least in oart and the passivation layer placed between the data wire and the pixel electrode has a thickness of 3 μm or more.
9. The LCD of claim 8 wherein the first and the second domain partitioning members comprise a protrusion pattern.
10. The LCD of claim 8 wherein the first and the second domain partitioning members comprise an opening pattern.
11. The LCD of claim 8 wherein one of the first and the second domain partitioning members comprises a protrusion pattern, and the other comprises an opening pattern.
12. A thin film transistor (“TFT”) array panel comprising:
a gate wire formed on an insulating substrate, the gate wire including gate lines, and first and second gate electrodes connected to the gate lines and spaced apart from each other by a predetermined distance;
a gate insulating layer covering the gate wire;
first and second semiconductor layers formed on the gate insulating layer opposite the first and the second gate electrodes, respectively;
a data wire including first and second data lines intersecting the gate lines to define pixel areas and spaced apart from each other by a predetermined distance, first and second source electrodes which are respective parts of the first and the second data lines, and first and second drain electrodes respectively facing the first and the second source electrodes;
a passivation layer with at least one contact hole for electrically connecting the first and the second drain electrodes to the pixel electrode; and
a pixel electrode electrically connected to the first and the second drain electrodes,
wherein the pixel electrode overlaps the data wire having the first and the second data lines at least in part and the passivation aver placed between the data wire and the pixel electrode has a thickness of 3 μm or more.
13. The TFT array panel of claim 12 wherein the first and the second drain electrodes are connected to each other.
14. The TFT array panel of claim 12 wherein the data wire further includes data line connectors, respectively formed at the upper and the lower half parts of the pixel area, to interconnect the first and the second data lines.
15. The TFT array panel of claim 12 further comprising a storage electrode line formed of the same layer as the gate lines and parallel to the gate lines.
16. The TFT array panel of claim 15 further comprising storage capacitor conductive patterns overlapped with the storage electrode lines.
17. The TFT array panel of claim 16 further comprising a conductor pattern connector connecting the first and the second drain electrodes to the storage capacitor conductive pattern.
18. The TFT array panel of claim 16 wherein the at least one contact hole is placed on the storage capacitor conductive pattern.
19. The TFT array panel of claim 12 wherein the first and second semiconductor layers and the data wire have the same planar shape except for areas between the first source electrode and the first drain electrode and between the second source electrode and the second drain electrode.