Method and apparatus to store delay locked loop biasing parameters
View Patent ↗A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.
1. An integrated circuit, comprising:
a clock path for carrying a clock signal;
a power supply path adapted to receive power from a power supply;
a delay locked loop connected to the power supply path, comprising:
a voltage-controlled delay line for generating a delayed clock signal dependent on an input thereto;
a phase detector for detecting a phase difference between the clock signal and the delayed clock signal; and
a bias-generator arranged to output a voltage to the input of the voltage-controlled delay line responsive to the phase detector;
an adjustment circuit operatively connected to the input of the voltage-controlled delay line, wherein the adjustment circuit is responsive to control information to adjust the voltage output by the bias-generator, wherein the control information comprises a binary word; and
a storage device adapted to store the control information to which the adjustment circuit is responsive.
wherein the adjustment circuit comprises a first switch to provide current flow between a first voltage provided by the power supply path and the input of the voltage-controlled delay line, and a second switch to provide current flow between a second voltage provided by the power supply path and the input of the voltage-controlled delay line.
2. The integrated circuit of claim 1 , wherein the adjustment circuit comprises a first p-channel transistor and a first n-channel transistor connected in series.
3. The integrated circuit of claim 2 , the adjustment circuit further comprising:
a second p-channel transistor connected in parallel with the first p-channel transistor; and
a second n-channel transistor connected in parallel with the first n-channel transistor, wherein the first p-channel transistor and second p-channel transistor are in series with the first n-channel transistor and second n-channel transistor.
4. The integrated circuit of claim 1 , wherein the storage device comprises a storage element selected from a group consisting of an electrically programmable fuse, an electrically programmable read only memory, an electrically erasable read only memory, a one time programmable memory, and a flash memory.
5. The integrated circuit of claim 1 , wherein the storage device comprises a storage element selected from a group consisting of a laser programmable fuse and a laser programmable anti-fuse.
6. The integrated circuit of claim 1 , wherein the control information comprises an instruction.
7. The integrated circuit of claim 1 , further comprising:
a test processor unit operatively coupled to the storage device and the adjustment circuit.
8. The integrated circuit of claim 7 , further comprising:
a tester adapted to communicate with the test processor unit, and read at least a portion of the control information in the storage device.
9. The integrated circuit of claim 7 , further comprising:
a tester adapted to communicate with the test processor unit, and write at least a portion of the control information in the storage device.
10. The integrated circuit of claim 1 , wherein the adjustment circuit is connected to the input of the voltage-controlled delay line with a wired-OR connection.
11. A method for post-fabrication treatment of a delay locked loop, comprising:
generating a delayed clock signal;
comparing the delayed clock signal to a clock signal;
adjusting the generating based on the comparing using a bias-generator;
generating a binary control word;
selectively adjusting an output of the bias-generator in the delay locked loop dependent on the binary control word;
operating the delay locked loop, wherein the selectively adjusting the output of the bias-generator modifies an operating characteristic of the delay locked loop; and
storing control information determined from the adjusting of the generating of the delay clock signal,
wherein the selectively adjusting the output of the bias-generator is performed by an adjustment circuit, wherein the adjustment circuit comprises a first switch to provide current flow between a first voltage and the output of the bias-generator, and a second switch to provide current flow between a second voltage and the output of the bias-generator.
12. The method of claim 11 , wherein the selectively adjusting the output of the bias-generator is performed by an adjustment circuit, wherein the adjustment circuit comprises a first p-channel transistor and a first n-channel transistor, wherein the first p-channel transistor and the first n-channel transistor are connected in series.
13. The method of claim 12 , the adjustment circuit further comprising:
a second p-channel transistor connected in parallel with the first p-channel transistor; and
a second n-channel transistor connected in parallel with the first n-channel transistor, wherein the first p-channel transistor and second p-channel transistor are in series with the first n-channel transistor and second n-channel transistor.
14. The method of claim 11 , wherein the storing comprises at least one selected from a group consisting of electrically programming a fuse, electrically programming a read only memory, electrically erasing a read only memory, programming a one time programmable memory, and programming a flash memory.
15. The method of claim 11 , wherein the storing comprises at least one selected from a group consisting of laser programming a fuse and laser programming an anti-fuse.
16. The method of claim 11 , wherein generating the binary control word is performed by a test processor unit.
17. The method of claim 11 , further comprising:
reading the control information using a test processor unit; and
operatively controlling the generating of the delay clock signal, with the test processor unit.
18. The method of claim 11 , further comprising:
reading the control information; and
instructing a test processor unit based on the control information to generate the binary control word.
19. The method of claim 11 , wherein the control information represents an offset in the output of the bias-generator.