IP Library Granted Patent US 7,245,633
Granted Patent B1
US 7,245,633 · App. 10/148,454 · Granted Jul 17, 2007

Multiplexing method for gigabit ethernet signals in the synchronous digital hierarchy

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Quick Facts
Patent No.
US 7,245,633
App. No.
10/148,454
Granted
Jul 17, 2007
Kind
B1
Abstract

A multiplexing method for Ethernet signals in the synchronous digital hierarchy, wherein the bit rate of a Gigabit Ethernet signal is reduced at the transmission end via 10B/8B decoding such that, after marking control words and data words which are to be transmitted in packets, the packets can be inserted in an STM-N signal.

Claims (40)

1. A system for inserting Ethernet signals into STM-N signals in a synchronous digital hierarchy, comprising:

parts for serial/parallel conversion of the Ethernet signals;

a decoder which receives the converted Ethernet signals word-by-word, carries out 10B/8B decoding of the Ethernet signals and marks control data and payload data; and

a packetizer following the decoder, wherein the packetizer:

combines a bit stream emitted from the decoder to form packets,

combines the packets to form VC-4 signals,

marks a start of a packet by a flag byte and adds a padding byte at an end of the packet, and

arranges information data between the flag byte and the padding byte, with a number of words of payload data arranged in an information field being divisible by 9, and including a length of m bytes.

2. A system for inserting Ethernet signals into STM-N signals in a synchronous digital hierarchy as claimed in claim 1 , wherein a logic value can be attached to the control data and payload data in the decoder.

3. A system for inserting Ethernet signals into STM-N signals in a synchronous digital hierarchy as claimed in claim 1 , further comprising:

a mapper for packing an output signal from the packetizer into eight signals, the signals being one of immediately successive signals and virtually concatenated signals; and

a multiplexer for attaching SDH-specific overhead information to an STM-N signal.

4. A system for forming Ethernet signals from an STM-N signal in a synchronous digital hierarchy, comprising:

a demultiplexer for separating overhead information from the STM-N signal;

a demapper for recovering a payload signal;

a depacketizer for identifying and separating flag and padding information, with payload data being produced at an output of the depacketizer at a bit rate as specified for STM-N signals; and

an encoder for forming a bit rate which is specified for Ethernet signals using 9B/10B coding.

5. A method for inserting Ethernet signals in an STM-N signal in a synchronous digital hierarchy, the method comprising the steps of:

serial/parallel converting the Ethernet signals;

supplying the Ethernet signals word-by-word to a decoder;

10B/8B decoding of the Ethernet signals; and

marking both control data and payload data;

arranging a flag byte at a start of a packet; and

arranging a padding byte at an end of the packet; and

arranging information data between the flag byte and the padding byte, with a number of words in an information field arranged between the flag byte and the padding byte being divisible by 9 and having a length of m bytes.

6. A method for inserting Ethernet signals in an STM-N signal in a synchronous digital hierarchy as claimed in claim 5 , the method further comprising the steps of:

combining a decoded bit stream at an output of the decoder into packets; and

combining the packets to form VC-4 signals.

7. A method for forming Ethernet signals from an STM-N signal in a synchronous digital hierarchy, the method comprising the steps of:

separating overhead information from the STM-N signal; and

matching a bit rate from payload data in the STM-N signal to a bit rate which corresponds to a bit rate of Ethernet signals, via 9B/10B coding.

8. A system for inserting Ethernet signals into STM-N signals in a synchronous digital hierarchy, comprising:

parts for serial/parallel conversion of the Ethernet signals;

a decoder which receives the converted Ethernet signals word-by-word, carries out 10B/8B decoding of the Ethernet signals and marks control data and payload data;

a packetizer following the decoder, wherein the packetizer:

combines a bit stream emitted from the decoder to form packets,

combines the packets in a subsequent step to form VC-4 signals,

marks a start of a packet by a flag byte and adds a padding byte at an end of the packet;

a mapper for packing an output signal from the packetizer into eight signals, the signals being one of immediately successive signals and virtually concatenated signals; and

a multiplexer for attaching SDH-specific overhead information to an STM-N signal.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Oct 26, 2018
From: CERBERUS BUSINESS FINANCE, LLC
To: XIEON NETWORKS S.A.R.L.
Reel/Frame 047335/0952 →
SECURITY INTEREST Recorded Dec 16, 2014
From: XIEON NETWORKS S.A R.L
To: CERBERUS BUSINESS FINANCE, LLC, AS COLLATERAL AGENT
Reel/Frame 034639/0201 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2013
From: NOKIA SIEMENS NETWORKS GMBH & CO. KG
To: XIEON NETWORKS S.A.R.L.
Reel/Frame 031719/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2008
From: SIEMENS AKTIENGESELLSCHAFT
To: NOKIA SIEMENS NETWORKS GMBH & CO. KG
Reel/Frame 020915/0503 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2002
From: MUELLER, HORST
To: SIEMENS AKTIENGESELLSCHAFT
Reel/Frame 013167/0441 →