Semiconductor device
View Patent ↗A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC 1 ) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC 2 ) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB 1 ), the level converter circuit (LSC 2 ) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.
1. A semiconductor device comprising:
a first circuit which operates on a first voltage of power supply and outputs a first signal with the amplitude of the first voltage of power supply;
a second circuit which operates a second voltage of power supply higher than the first voltage of power supply; and
a level converter which operates on the first and second voltages of power supply, converts said first signal to a second signal with the amplitude of said second voltage of power supply, and outputs the second signal to said second circuit,
said level converter comprising a voltage-up circuit which operates on the first voltage of power supply and steps up the amplitude of said first signal, a level converter circuit which operates on the second voltage of power supply and converts an output signal from said voltage-up circuit to said second signal with the amplitude of the second voltage of power supply, and means for holding a voltage level output from the level converter circuit.
2. A semiconductor device according to claim 1 , wherein said means for holding a voltage level output from the level converter is a latch circuit consisting of two stages of inverters.
3. A semiconductor device according to claim 2 , wherein said level converter circuit further includes a power control circuit which controls power supply to the inverters constituting said latch circuit.
4. A semiconductor device according to claim 3 , wherein said power control circuit comprises a first p-channel MOSFET whose gate is connected to ground potential and a first n-channel MOSFET whose gate is connected to said second voltage of power supply;
wherein said first p-channel MOSFET is connected in series to the source of a p-channel MOSFET component of an inverter of said latch circuit and said first n-channel MOSFET is connected in series to the source of an n-channel MOSFET component of the inverter.
5. A semiconductor device according to claim 3 , wherein said power control circuit further comprises a second p-channel MOSFET whose gate is connected to a voltage equaling a p-channel MOSFET threshold voltage above said ground voltage and a second n-channel MOSFET whose gate is connected to a voltage equaling said second voltage of power supply less an n-channel MOSFET threshold voltage;
wherein said second p-channel MOSFET is connected in series to the source of a P-channel MOSFET component of an inverter of said latch circuit and said second n-channel MOSFET is connected in series to the source of an n-channel MOSFET component of the inverter.
6. A semiconductor device according to claim 3 , wherein said power control circuit further comprises a third p-channel MOSFET whose gate is connected to a voltage equaling the p-channel MOSFET threshold voltage above said ground voltage and a third n-channel MOSFET whose gate is connected to a voltage equaling said third voltage of power supply less the n-channel MOSFET threshold voltage;
wherein said third p-channel MOSFET is connected in series to the source of a P-channel MOSFET component of an inverter of said latch circuit and said third n-channel MOSFET is connected in series to the source of an n-channel MOSFET component of the inverter.
7. A semiconductor device according to claim 3 , wherein said power control circuit is controlled by a power control signal that is derived from signals output from said level converter circuit.
8. A semiconductor device according to claim 7 , wherein said power control signal is a signal obtained from exclusive OR of a signal to which the first signal input from said first circuit was amplitude converted by said level converter circuit and a signal that was amplitude converted by said level converter circuit just before said first signal was input.
9. A semiconductor device according to claim 8 , wherein said power control signal is a small amplitude signal that is obtained by letting said signal obtained from exclusive OR pass through an inverter of small potential amplitude.
10. A semiconductor device according to claim 9 , wherein said inverter of small potential amplitude consists of a p-channel MOSFET and an n-channel MOSFET;
wherein an n-channel MOSFET with its drain and gate being short-circuited is connected in series to the source of said p-channel MOSFET and a p-channel MOSFET with its drain and gate being short-circuited is connected in series to the source of said n-channel MOSFET.
11. A semiconductor device according to claim 9 , wherein said inverter of small potential amplitude consists of a p-channel MOSFET and an n-channel MOSFET;
wherein a p-channel MOSFET with its drain and gate being short-circuited is connected in series to the source of said p-channel MOSFET and an n-channel MOSFET with its drain and gate being short-circuited is connected in series to the source of said n-channel MOSFET.
12. A semiconductor device according to claim 8 , wherein said power control circuit comprises the first p-channel MOSFET whose gate is connected to ground potential, the first n-channel MOSFET whose gate is connected to said second voltage of power supply, a forth p-channel MOSFET connected in series to the drain of said first p-channel MOSFET, and a fourth n-channel MOSFET connected in series to the drain of said first n-channel MOSFET;
wherein a source-drain path of said fourth p-channel MOSFET is connected to the drain of a p-channel MOSFET component of an inverter of said latch circuit, a source-drain path of said fourth n-channel MOSFET is connected to the drain of an n-channel MOSFET component of the inverter of said latch circuit, a signal of inversion of said signal obtained from exclusive OR is input to said fourth p-channel MOSFET, and said signal obtained from exclusive OR is input to said fourth n-channel MOSFET.