Multiport-RAM memory device
View Patent ↗The invention relates to a multiport-RAM memory device, comprising a RAM memory unit ( 1 ), a number of serial/parallel converters ( 5, 6, 7 ) and a parallel/serial converter ( 10 ), for converting serial signals into parallel signals. Said multiport-RAM memory device further comprises a control unit ( 11 ) and two timeslot allocation devices ( 8, 9 ), whereby an emulation of a number of connections by using the simple RAM memory unit ( 1 ) may be achieved. Furthermore, a power controller ( 12 ) can significantly reduce the power demand.
1. A multiport RAM memory device, comprising:
a RAM memory unit having an address/control, a read port and a write port for a first time division multiplex system;
an address serial/parallel converter for converting a multiplicity of serial address signals of a second time division multiplex system into a multiplicity of parallel address signals of the first time division multiplex system;
a selection serial/parallel converter for converting a multiplicity of serial selection signals of the second time division multiplex system into a multiplicity of parallel selection signals of the first time division multiplex system;
a data input serial/parallel converter for converting at least one serial data input signal of the second time division multiplex system into at least one parallel data input signal of the first time division multiplex system;
a first time slot assignment unit for selectively feeding the parallel address signals, lying in predetermined time slots of the first time division multiplex system, to the address/control port of the RAM memory unit;
a second time slot assignment unit for assigning parallel data output signals, read out at the read port of the RAM memory unit, into predetermined time slots of the first time division multiplex system;
a parallel/serial converter for converting the multiplicity of parallel data output signals of the first time division multiplex system into a multiplicity of serial data output signals of the second time division multiplex system; and
a control unit for controlling the first and second time slot assignment units in a manner dependent on the multiplicity of parallel selection signals,
wherein the control unit drives the second time slot assignment unit so as to compensate for a temporal delay during read-out of the parallel data output signals from the RAM memory unit.
2. The multiport RAM memory device as claimed in claim 1 , further comprising
a power control unit for controlling a power consumption of the RAM memory unit in a manner dependent on the control unit.
3. The multiport RAM memory device as claimed in claim 2 , wherein
the power control unit controls the power consumption by switching on/off a clock signal for the RAM memory unit for a respective time slot in the first time division multiplex system.
4. The multiport RAM memory device as claimed in claim 1 , wherein
the serial/parallel converters and the parallel/serial converter are synchronized by a synchronizing pulse.
5. The multiport RAM memory device as claimed in claim 1 , wherein
the control unit includes a finite state machine.
6. The multiport RAM memory device as claimed in claim 1 , further comprising
a speech memory in a time switching unit of a switching network in a digital telecommunications switching system.
7. The multiport RAM memory device as claimed in claim 1 , wherein
the multiplicity of serial address signals and the multiplicity of serial selection signals constitute a multiplicity of control word signals of a multiplicity of connecting memories in a switching network.
8. The multiport RAM memory device as claimed in claim 1 , wherein
the first time division multiplex system has n data channels for the realization of n ports.
9. The multiport RAM memory device as claimed in claim 8 , wherein
the second time division multiplex system has m data channels, a data input signal being assigned to a predetermined write data channel of the n data channels.
10. The multiport RAM memory device as claimed in claim 9 , wherein
further n−1 n data channels are assigned to the n−1 read data channels or to the n−1 address signals and to the n−1 data output channels or to n−1 data output signals.
11. The multiport RAM memory device as claimed in claim 8 , wherein n=5.
12. The multiport RAM memory device as claimed in claim 9 , wherein m=2304.