System and method for adjusting group delay

1. A group delay adjusting circuit comprising:

a first stub matching structure coupled to a microstrip input transmission line;

a first DC blocking capacitor having a first terminal coupled to the microstrip input transmission line, and a second terminal;

a main transmission line having a first terminal coupled to the second terminal of the first DC blocking capacitor, a second terminal, a third terminal along its length, a fourth terminal along its length, and a fifth terminl along its length;

a first varactor diode having a first terminal coupled to the fifth terminal of the main transmission line, and a second terminal coupled to a ground;

a first high impedence line having a first terminal coupled to the third terminal of the main transmission line, and a second terminal;

a first RF by pass capacitor having a first terminal coupled to the second terminal of the first high impedance line and a first signal input pad, and a second terminal coupled to ground;

a second DC blocking capacitor having a first terminal coupled to the second terminal of the main transmission line, and a second terminal;

a second stub matching structure coupled to a microstrip output transmission line, and to the second terminal of the second DC blocking capacitor;

a third DC blocking capacitor having a first terminal coupled to the fourth terminal of the main transmission line, and a second terminal;

a transmission line of a quarter wavelength at a frequency of operation having a first terminal at a first end coupled to the second terminal to the third DC blocking capacitor, a second terminal at a second end, and a third terminal along its length;

a second varactor diode having a first terminal coupled to the second terminal of the transmission line of a quarter wavelength at a frequency of operation, and a second terminal coupled to the ground;

a second high impedance transmission line having a first terminal coupled to the third terminal of the transmission line of a quarter wavelength at a frequency of operation, and a second terminal; and

a second RF bypass capacitor having a first terminal coupled to the second terminal of the high impedance transmission line and to a second signal input pad, and a second terminal coupled to the ground.

2. A group delay adjusting circuit comprising:

a first stub matching structure coupled to a microstrip input transmission line;

a first DC blocking capacitor having a first terminal coupled to the microstrip input transmission line, and a second terminal;

a main transmission line having a first terminal coupled to the second terminal of the first DC blocking capacitor, a second terminal, a third terminal along its length, a fourth terminal along its length, and a fifth terminal along its length;

a first varactor diode having a first terminal coupled to the fifth terminal of the main transmission line, and a second terminal coupled to a ground;

a second DC blocking capacitor having a first terminal coupled to the third terminal of the main transmission line, and having a second terminal;

a second stub matching structure coupled to the second terminal of the second DC blocking capacitor;

a third DC blocking capacitor having a first terminal coupled to the fourth terminal of the main transmission line, and having a second terminal;

a T-shaped microstrip structure having a first terminal coupled to the second terminal of the third DC blocking capacitor, a second terminal and a third terminal;

a first resistor having a first terminal coupled to the second terminal of the T-shaped microstrip structure, and a second terminal;

a first RF by pass capacitor having a first terminal coupled to the second terminal of the first resistor and a first signal input pad, and having a second terminal coupled to ground;

an inductor having a first terminal coupled to the third terminal of the T-shaped microstrip structure and having a second terminal;

a second varactor diode having a first terminal coupled to the second terminal of the inductor, and a second terminal coupled to the ground;

a second resistor having a first terminal coupled to the fifth terminal of the microstrip output transmission line, and having a second terminal; and

a second RF bypass capacitor having a first terminal coupled to the second terminal of the second resistor and to a second signal input pad, and having a second terminal coupled to the ground.

3. A method of adjusting a group delay adjusting circuit comprising:

applying a signal to the group delay adjusting circuit

applying a capacitive control signal to adjust a first variable capacitance;

adjusting the first variable capacitance by applying the capacitive control signal to the first variable capacitance;

applying an inductive control signal to a second variable capacitance; and

adjusting the second variable capacitance by applying the inductive control signal to the second variable capacitance

measuring a group delay of the signal prior to the step of adjusting the first variable capacitance.

4. A variable inductance circuit comprising

a virtual inductor; and

a bias network coupled to the virtual inductor, wherein the bias network comprises:

a series impedance including a first terminal coupled to the quarter wavelength transmission line at a high impedance point and a second terminal coupled to an inductive control signal;

a first shunt capacitance having a first terminal coupled to the second terminal of the transmission line, and a second terminal coupled to a ground.

5. The variable inductance of claim 4 , wherein the series impedance comprises a high impedance transmission line.

6. The variable inductance of claim 4 , further comprising second capacitor having a first terminal coupled to a point on the high impedance transmission line, and a second terminal coupled to ground.

7. The variable inductance of claim 6 , wherein the high impedance transmission line is a microstrip transmission line.

8. The variable inductance of claim 7 , wherein the high impedance transmission line is a coaxial transmission line.

9. The variable inductance of claim 4 , wherein the series impedance comprises a series inductance.

10. The variable inductance of claim 4 , wherein the series impedance comprises a wire having a ferrite bead disposed about the wire.

11. The variable inductance of claim 4 , wherein the inductive control signal is a voltage.