Semiconductor integrated circuit device

1. A semiconductor integrated circuit device comprising:

a first circuit including an MIS transistor formed on a semiconductor substrate;

a second circuit including an MIS transistor formed on said semiconductor substrate which outputs an oscillation signal;

a substrate bias control circuit which controls a substrate bias supplied to a well of said MIS transistor of said first circuit and a well of said MIS transistor of said second circuit; and

a buffer circuit,

wherein, said substrate bias control circuit receives a reference clock and controls a value of said substrate bias so that a frequency of said reference clock coincides with a frequency of said oscillation signal output from said second circuit, and a substrate bias controlled by said substrate bias control circuit is supplied to said well of said MIS transistor of said first circuit via said buffer circuit, wherein a substrate bias is supplied to said well of said MIS transistor of said second circuit without being via said buffer circuit.

2. A semiconductor integrated circuit device according to claim 1 , wherein said buffer circuit receives a substrate bias controlled by said substrate bias control circuit with a first output impedance and outputs with an output impedance smaller than said first impedance to said first circuit.

3. A semiconductor integrated circuit device according to claim 1 , wherein said semiconductor integrated circuit device has a first state and a second state, and said buffer circuit supplies a substrate bias controlled by said substrate bias control circuit to said well of said MIS transistor of said first circuit in said first state, and said buffer circuit supplies a substrate bias deeper than that in said first state to said well of said MIS transistor of said first circuit in said second state.

4. A semiconductor integrated circuit device, comprising:

a first circuit including a MIS transistor formed on a semiconductor substrate;

a second circuit including a MIS transistor formed on said semiconductor substrate;

a third circuit including a MIS transistor formed on said semiconductor substrate which outputs an oscillation signal;

a substrate bias control circuit which controls a substrate bias supplied to a well of said MIS transistor of said first circuit, a well of said MIS transistor of said second circuit and a well of said MIS transistor of said third circuit;

a plurality of substrate bias wirings which supply said substrate bias; and

first and second buffer circuits, wherein said substrate bias control circuit receives a reference clock and controls a value of said substrate bias so that a frequency of said reference clock coincides with a frequency of said oscillation signal output from said third circuit, and a substrate bias controlled by said substrate bias control circuit is supplied to said well of said MIS transistor of said first circuit from said substrate bias wirings via said first buffer circuit, and a substrate bias controlled by said substrate bias control circuit is supplied to said well of said MIS transistor of said second circuit from said substrate bias wirings via said second buffer circuit.

5. A semiconductor integrated circuit device according to claim 4 , further comprising a third buffer circuit, and wherein a substrate bias controlled by said substrate bias control circuit is supplied to said substrate bias wirings via said third buffer.

6. A semiconductor integrated circuit device according to claim 4 , wherein a substrate bias controlled by said substrate bias control circuit is supplied to said well of said MIS transistor of said third circuit without being via said third buffer circuit.

7. A semiconductor integrated circuit device according to claim 4 , wherein each of said first and second buffer circuits receives a substrate bias controlled by said substrate bias control circuit with a first outout impedance and outputs with an impedance output smaller than said first impedance to said substrate bias wiring.

8. A semiconductor integrated circuit device according to claim 4 , wherein said first and second circuits have a first state and a second state, respectively, and said first buffer circuit supplies a substrate bias controlled by said substrate bias control circuit to said well of said MIS transistor of said first circuit in said first state, and said first buffer circuit supplies a substrate bias deeper than that in said first state to said well of said MIS transistor of said first circuit in said second state, and said second buffer circuit supplies a substrate bias controlled by said substrate bias control circuit to said well of said MIS transistor of said second circuit in said first state, and said second buffer circuit supplies a substrate bias deeper than that in said first state to said well of said MIS transistor of said second circuit in said second state.

9. A semiconductor integrated circuit device according to claim 5 , wherein said semiconductor integrated circuit device has a first state and a second state, and said third buffer circuit supplies a substrate bias controlled by said substrate bias control circuit to said substrate bias wirings in said first state, and said third buffer circuit supplies a substrate bias deeper than that in said first state to said substrate bias wirings in said second state.

10. A semiconductor integrated circuit device comprising:

a plurality of circuit blocks including MIS transistors formed on a semiconductor substrate;

a plurality of substrate bias switch circuits, each of the substrate bias switch circuits being provided for a corresponding one of the circuit blocks;

an oscillation output circuit to output a frequency-variable oscillation signal, including MIS transistors formed on the semiconductor substrate;

a buffer circuit;

a control circuit; and

a power control circuit,

wherein the control circuit is supplied with a clock signal and the frequency- variable oscillation signal;

wherein the control circuit outputs a first control signal by comparing a frequency of the clock signal and a frequency of the frequency-variable oscillation signal,

wherein a frequency of the frequency-variable oscillation signal is controlled by controlling threshold voltages of MIS transistors by the first control signal,

wherein the buffer circuit receives the first control signal and outputs a second control signal corresponding to the first control signal,

wherein each of the substrate bias switc hcircuits receives the second control signal and outputs a third control signal corresponding to the second control signal,

wherein the third control signal is inputted to the circuit block to control threshold voltages of MIS transistors of the circuit block,

wherein the buffer circuit controls a value of the second control signal to be a value not related to a value of the first control signal by receiving a first power control signal from the power control ciruit in order to control the plurality of the circuit blocks to be in a power-saving state, and

wherein each of the substrate bias switch circuits controls a value of the third contrl signal to be a value not related to a value of the second control signal by receiving a second power control signal from the power control circuit in order to control the circuit block corresponding to the substrate bias switch circuit to be in a power-saving state.

11. The semiconductor integrated circuit device according to claim 10 ,

wherein the first control signal is inputted to the buffer circuit with a first impedance, and wherein the buffer circuit outputs the second control signal with a second impedance lower than the first impedance.

12. The semiconductor integrated circuit device according to claim 10 ,

wherein the second control signal is inputted to the substrate bias switch circuits with a third impedance, and wherein the substrate bias switch circuits output the third control signal with a fourth impedance lower than the thrid impedance.

13. The semiconductor integrated circuit device according to claim 10 ,

wherein the first control signal controls substrate bias voltages of MIS transistors of the oscillation output circuit, and

wherein the third control signal controls substrate bias voltages of MIS transistors of the circuit block.

14. The semiconductor integrated circuit device according to claim 10 ,

wherein the buffer circuit receives the first control signal and outputs the second control signal with a gain of 1 , and

wherein the substrate bias switch circuit receives the second control signal and outputs the third control signal with a gain of 1 .

15. The semiconductor integrated circuit device according to claim 10 ,

wherein threshold voltages of the MIS transistors of the circuit block when the third control signal has a value which is not related to the value of the second control signal are higher than threshold voltages of the MIS transistors of the circuit block when the third control signal has a value which is related to the value of the second control signal.