Register window flattening logic for dependency checking among instructions

1. A method for processing a plurality of instructions in a computer system, comprising:

flattening an n-bit value stored in a first architectural register of a first instruction in a register window into an x-bit value dependent on a current window pointer to the register window, wherein x is greater than n, and wherein the x-bit value corresponds to the first architectural register;

flattening a p-bit value stored in a second architectural register of a second instruction in the register window into a q-bit value dependent on the current window pointer, wherein q is greater than p, and wherein the q-bit value corresponds to the second architectural register; and

checking a register dependency among the first instruction and the second instruction using the x-bit value and the q-bit value.

2. The method of claim 1 , wherein flattening the n-hit value comprises:

generating a first plurality of select signals dependent on the n-bit value;

generating a second plurality of select signals dependent on the current window pointer; and

generating the x-bit value dependent on the first plurality and second plurality of select signals.

3. A method for processing a plurality of instructions in a computer system, comprising:

step for flattening an n-bit value stored in a first architectural register of a first instruction in a register window into an x-bit value dependent on a current window pointer to the register window, wherein x is greater than n, and wherein the x-bit value corresponds to the flit architectural register;

step for flattening a p-bit value stored in a second architectural register of a second instruction in the register window into a q-bit value dependent on the current window pointer, wherein q is greater than p, and wherein the q-bit value corresponds to the second architectural register; and

step for register dependency checking among the first instruction and the second instruction using the x-bit value and the q-bit value.

4. A computer system, comprising:

a processor;

a memory;

instructions, residing in the processor and executable on the processor, for flattening an n-bit value in a first architectural register of a first instruction in a register window into an x-bit value dependent on a current window pointer to the register window, wherein x is greater than n, and wherein the x-bit value corresponds to the first architectural register;

instructions, residing in the memory and executable on the processor, for flattening a p-bit value stored in a second architectural register of a second instruction in the register window into a q-bit value dependent on the current window pointer, wherein q is greater than p, and wherein q-bit value corresponds to the second architectural register; and

instructions, residing in the memory and executable on the processor, for using the x-bit value and the q-bit value to check for a dependency among the first instruction and the second instruction.

5. A computer-readable medium having recorded therein instructions executable by processing, the instructions for:

flattening an n-bit value stored in a first architectural register of a first instruction in a register window into an x-bit value dependent on a current window pointer to the register window, wherein x is greater than n, and wherein the x-bit value corresponds to the first architectural register;

flattening a p-bit value stored in a second architectural register of a second instruction in the register window into a q-bit value dependent on the current window pointer, wherein q is greater than p, and wherein the q-bit value corresponds to the second architectural register; and

register dependency checking among the first instruction and the second instruction using the x-bit value and the q-bit value.