Conditional branch instruction capable of testing a plurality of indicators in a predicate register
View Patent ↗A method of conditionally executing branch instructions which comprise an opcode field defining a type of test to be applied to determine whether or not to execute a branch operation, a control field designating a control store holding a plurality of indicators and a destination field holding information on a branch target address. The method comprises determining from the opcode field whether or not the test will check the state of one indicator or a plurality of indicators in the designated control store, accessing the designated control store to check the state of said one or said plurality of indicators depending on the determination, and generating a branch target address using information in the destination field in dependence on the state of the or each indicator checked.
1. A system for conditionally executing branch operations, comprising:
a control store including predicate registers, at least one of the predicate registers configured to control Single Instruction Multiple Data (SIMD) lane execution of a plurality of SIMD lanes expressed in an instruction, wherein the at least one of the predicate registers comprises a plurality of bits, each bit being configured to control a corresponding lane of the plurality of SIMD lanes; and
a branching circuit configured
to receive a conditional branching instruction designating a predicate register and any one bit of the plurality of bits of the designated predicate register and
to conditionally perform a branch operation based on a branching condition, wherein the branching condition is satisfied when the designated one bit of the designated predicate register is in a predetermined state.
2. The system of claim 1 , further comprising:
fetch and decode circuitry to fetch and decode a plurality of instructions from an instruction store, the plurality of instructions including the conditional branching instruction.
3. The system of claim 1 , wherein the conditional branching instruction indicates a type of test.
4. The system of claim 1 , further comprising a branch target address generation circuit configured to generate a branch target address.
5. The system of claim 4 , further comprising a program counter, wherein the branch target address generation circuit is configured to replace a value of the program counter with a new value from a data store.
6. The system of claim 4 , further comprising a program counter, wherein the branch target address generation circuit is configured to modify a value of the program counter based on an immediate value.
7. The system of claim 1 , further comprising a branch target address generation circuit configured to generate a branch target address when the branching condition is satisfied.
8. The system of claim 1 , wherein the conditional branching instruction includes a field indicating a likelihood of the branch operation being performed.
9. The system of claim 1 , further comprising a logic circuit configured to set the designated one bit to the predetermined state based on a test condition.
10. The system of claim 1 , further comprising a logic circuit configured to set the designated one bit to the predetermined state based on a plurality of sequential test conditions.
11. The system of claim 1 , wherein the branching circuit is further configured to receive a second conditional branching instruction designating all bits of the plurality of bits of a predicate register.
12. The system of claim 1 , wherein the branching circuit is further configured
to receive a second conditional branching instruction designating a predicate register and
to conditionally perform a second branch operation based on a second branching condition, wherein the second branching condition is satisfied only when all of the bits of the designated predicate register are in a predetermined state.
13. The system of claim 1 , further comprising:
a logic circuit configured to set the designated one bit and zero or more additional bits of the designated predicate register to the predetermined state based on a test condition.
14. The system of claim 13 , wherein the designated one bit and zero or more additional bits of the designated predicate register correspond to a packed object.
15. The system of claim 1 , wherein the designated predicate register is divided into groups of bits corresponding to a number of packed objects.
16. The system of claim 15 , wherein bits of one of the groups of bits are set to the predetermined state based on a test condition when a degree of packing of the packed objects is less than a quantity of the plurality of SIMD lanes.
17. A method comprising:
receiving, by one or more computing devices, a conditional branching instruction designating:
a predicate register configured to control Single Instruction Multiple Data (SIMD) lane execution of a plurality of SIMD lanes expressed in an instruction, the predicate register comprising a plurality of bits, each bit being configured to control a corresponding lane of the plurality of SIMD lanes; and
any one bit of the plurality of bits of the designated predicate register; and
conditionally performing, by the one or more computing devices, a branch operation based on a branching condition that is satisfied based on the designated one bit of the designated predicate register is in a predetermined state.