Methods and apparatus for speculative probing of a remote cluster
View Patent ↗According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or a home cluster. A speculative probe associated with a particular memory line is transmitted to the remote cluster before the cache access request associated with the memory line is serialized at a home cluster. When a non-speculative probe is received at a remote cluster, the information associated with the response to the speculative probe is used to provide a response to the non-speculative probe.
1. A computer system, comprising:
a request cluster including a plurality of interconnected request cluster processors and a request cluster cache coherence controller;
a home cluster including a plurality of interconnected home processors, a serialization point, and a home cache coherence controller; and
a remote cluster including a plurality of interconnected remote processors and a remote cache coherence controller, wherein the remote cluster is configured to receive a first probe corresponding to a cache access request from a request cluster processor in the request cluster and a second probe corresponding to the cache access request from the home cluster.
2. The computer system of claim 1 , wherein the first probe is a speculative probe.
3. The computer system of claim 2 , wherein the second probe is a non-speculative probe.
4. The computer system of claim 2 , wherein the results of the first probe are used in a probe response corresponding to the second probe.
5. The computer system of claim 4 , wherein the first probe is dropped if the second probe is received before the first probe.
6. The computer system of claim 4 , wherein the first probe is dropped if a third probe corresponding to a memory line associated with the cache access request is received before the first probe.
7. The cache coherence controller of claim 6 , wherein the request cluster cache coherence controller is constructed to act as an aggregate remote cache.
8. The cache coherence controller of claim 6 , wherein the request cluster cache coherence controller is constructed to act as a probing agent pair.
9. The cache coherence controller of claim 6 , wherein the request cluster cache coherence controller is constructed to act as a remote memory.
10. The cache coherence controller of claim 6 , wherein the request cluster cache coherence controller is constructed to act as a remote processor.
11. A method for a cache coherence controller to manage data access in a multiprocessor system, the method comprising:
receiving a cache access request from a request cluster processor associated with a request cluster;
forwarding the cache access request to a home cluster, the home cluster including a home cluster cache coherence controller and a serialization point; and
sending a probe associated with the cache request to a remote cluster.
12. The method of claim 11 , wherein sending the probe associated with the cache request comprises sending a probe to a remote cluster cache coherence controller before a memory line associated the probe is locked.
13. The method of claim 11 , wherein a plurality of request cluster processors in the request cluster share a memory address space with a plurality of home processors in the home cluster.
14. The method of claim 11 , wherein sending the probe to the remote cluster comprises sending a probe to the remote node before a request associated with the probe is received at a memory access serialization point.
15. A computer system, comprising:
a first cluster including a first plurality of processors and a first cache coherence controller, the first plurality of processors and the first cache coherence controller interconnected in a point-to-point architecture;
a second cluster including a second plurality of processors and a second cache coherence controller, the second plurality of processors and the second cache coherence controller interconnected in a point-to-point architecture, the first cache coherence controller coupled to the second cache coherence controller;
wherein the first cache coherence controller is configured to receive a cache access request originating from the first plurality of processors and send a probe to a third cluster including a third plurality of processors before the cache access request is received by a serialization point in the second cluster.
16. The computer system of claim 15 , wherein the memory access serialization point is a memory controller in the second cluster.
17. The computer system of claim 16 , wherein the probe is associated with the memory line corresponding to the cache access request.
18. The computer system of claim 15 , wherein the third cluster includes a third cache coherence controller.
19. The computer system of claim 17 , wherein the third cache coherence controller is further configured to receive a probe originating from the second cluster and respond to the probe originating from the second cluster using information obtained from the probe of the first plurality of processors.
20. The computer system of claim 19 , further comprising a pending buffer associated with the first cache coherence controller.
21. A computer system, comprising:
a first cluster including a first plurality of processors and a first cache coherence controller, the first plurality of processors and the first cache coherence controller interconnected in a point-to-point architecture;
a second cluster including a second plurality of processors and a second cache coherence controller, the second plurality of processors and the second cache coherence controller interconnected in a point-to-point architecture, the first cache coherence controller coupled to the second cache coherence controller and constructed to receive a cache access request originating from the first plurality of processors and send a probe to a third cluster including a third plurality of processors before a memory line associated with the cache access request is locked.
22. A cache coherence controller, the cache coherence controller comprising:
interface circuitry coupled to a request cluster processor in a request cluster and a remote cluster cache coherence controller in a remote cluster;
a protocol engine coupled to the interface circuitry, the protocol engine configured to receive a cache access request from the request cluster processor and speculatively probe a remote node in the remote cluster.
23. The cache coherence controller of claim 22 , wherein the protocol engine is further configured to speculatively probe the remote node by sending a probe to the remote node before a memory line associated the probe is locked.
24. The cache coherence controller of claim 22 , wherein the request cluster processor shares a memory address space with a remote cluster processor.
25. The cache coherence controller of claim 24 , wherein the request cluster includes a plurality of processors interconnected in a point-to-point architecture.
26. The cache coherence controller of claim 24 , wherein the remote cluster includes a plurality of processors interconnected in a point-to-point architecture.
27. The cache coherence controller of claim 22 , wherein the protocol engine is further configured to speculatively probing a remote node by sending a probe to the remote cache coherence controller associated with the remote node before a request associated with the probe is received at a memory access serialization point.
28. The cache coherence controller of claim 27 , wherein the memory access serialization point is a memory controller in a home cluster.
29. The cache coherence controller of claim 22 , wherein the cache coherence controller is constructed to act as an aggregate remote cache.
30. The cache coherence controller of claim 22 , wherein the cache coherence controller is constructed to act as a probing agent pair.
31. The cache coherence controller of claim 22 , wherein the cache coherence controller is constructed to act as a remote memory.
32. The cache coherence controller of claim 22 , wherein the cache coherence controller is constructed to act as a remote processor.
33. The cache coherence controller of claim 22 , wherein the protocol engine, the request cluster processor, and the remote cluster processor support a coherence protocol.
34. The cache coherence controller of claim 33 , wherein the request cluster cache coherence controller is coupled to the remote cluster cache coherence controller through a point-to-point architecture.
35. The cache coherence controller of claim 33 , wherein the request cluster cache coherence controller is coupled to the remote cluster cache coherence controller through a switch architecture.
36. A cache coherence controller, comprising:
means for receiving a cache access request from a request cluster processor associated with a request cluster;
means for forwarding the cache access request to a home cluster, the home cluster including a home cluster cache coherence controller and a serialization point; and
means for sending a probe associated with the cache request to a remote cluster.