Method of communicating data via a bus and bus system for implementing the method
View Patent ↗In a method of communicating data via a bus between several modules connected to the bus in accordance with the source synchronous clock principle the data is applied from the modules to a data bus as controlled by the system clock signal A source clock signal generated by each of the modules is communicated spaced in time from the data on a source clock line. The time spacing between the data applied by a module to the data bus and the source clock signal generated by this module and applied to the source clock line can be varied as a function of characteristic parameters of the modules connected to the bus with the aid of an adjustable delay member.
1. A method of communicating data via a bus connected to a module to form a system, comprising the steps of:
generating a source clock signal by the module;
applying data to a data bus as controlled by a system clock signal from the module;
applying said source clock signal to a source clock line spaced in time from the data; and
varying the time spacing between the data from the module and the source clock signal generated by the module and applied to the said clock line as a function of a data transfer rate of the bus.
2. A bus system for communicating data between modules by a bus;
a module for applying said data to said bus in accordance with a system clock signal;
said module generating a source clock signal and applying said system clock signal on a source clock line; and
a delay line positioned between said module and said source clock line having a delay time adjustable by a control line.
3. The bus system as set forth in claim 2 , wherein said control signal is a digital signal by which said delay time can be set to one of several discrete values.
4. The bus system as set forth in claim 2 , wherein said control signal is an analog signal by which said delay time can be set to a value with a predefined range.