Method of first interleaving of a two interleaver transmitter
View Patent ↗The present invention involves padding the bit sequence in the first interleaver. The present method adds to an end of the bit sequence a sufficient number of padding bits L to permit modulus 16 operation of the bit sequence. After performing the interleaving, L bits are removed from an end of the interleaved sequence. This allows the interleaving to be performed in 16-bit segments simultaneously.
1. A method of interleaving of a first interleaver of a two interleaver forward error correction transmitter, the method comprising:
prior to the first interleaving of a sequence of bits, adding to an end of the bit sequence a sufficient number L of padding bits to permit modulus sixteen operation of the bit sequence;
performing the first interleaving of the bit sequence;
removing L bits from an end of the interleaved bit sequence; and
providing the interleaved bit sequence to a second interleaver of the transmitter.
2. The method of claim 1 , including performing the interleaving in 16-bit segments simultaneously.
3. The method of claim 1 , wherein the adding includes adding randomly alternating zero and one bits.
4. A method of interleaving of a first interleaver of a two interleaver forward error correction transmitter, the method comprising:
prior to interleaving a sequence of bits, adding to an end of the bit sequence a sufficient number L of padding bits to permit modulus sixteen operation of the bit sequence;
performing interleaving of the bit sequence; and
removing L bits from an end of the interleaved bit sequence, wherein the number L, as determined by:
L= 16−Mod 16 ( X i )
where, Mod 16 represent modulus sixteen operation, and X i is the input bit sequence.
5. The method of claim 1 , the L bits are added and removed from the same end of the sequence.
6. The method of claim 1 , the L bits are added and removed from opposite ends of the sequence.
7. The method of claim 1 , wherein the interleaving is performed in software.
8. The method of claim 1 , wherein the method is performed without forming a matrix of the bit sequence.
9. An apparatus including an interleaver or deinterleaver performing the method of claim 1 .
10. The apparatus of claim 9 , wherein the apparatus includes software for performing the method of claim 1 .
11. The apparatus of claim 9 , wherein the method of claim 1 is performed in the apparatus without forming a matrix of the bit sequence.