Integrated circuit package substrate with high density routing mechanism
View Patent ↗A semiconductor substrate having high density signal routing is provided. The semiconductor substrate may include first signal traces electrically connected to a first row of signal bonding pads and routed on a first layer of the substrate. In addition, the substrate may include second signal traces electrically connected to a second row of signal bonding pads and routed on a second layer of the substrate. The first layer may be arranged in a strip line configuration, and the second layer may be arranged in a micro strip line configuration. Alternatively, the second signal traces may be arranged in a strip line configuration. In an embodiment, the first and second signal traces may be routed as differential pairs with approximately equal trace lengths. In another embodiment, all of the first and second signal traces may be routed as differential pairs.
1. A semiconductor substrate, comprising:
signal bonding pads formed upon an upper surface of the substrate in a first row and a second row, wherein an area on the upper surface is adapted to receive an integrated circuit;
first signal traces electrically connected to the first row of signal bonding pads and routed on a first layer of the substrate;
second signal traces electrically connected to the second row of signal bonding pads and routed on a second layer of the substrate, wherein the second signal traces comprise vias arranged in adjacent pairs with gaps between the adjacent pairs, and wherein the gaps provide continuity for a ground plane extending within the gaps.
2. The substrate of claim 1 , wherein the first row of signal bonding pads is spaced farther from the area than the second row of signal bonding pads.
3. The substrate of claim 1 , wherein the first and second signal traces are routed as differential pairs with approximately equal trace lengths.
4. The substrate of claim 1 , wherein all of the first and second traces are routed as differential pairs.
5. The substrate of claim 1 , wherein the first layer is formed across the upper surface, and wherein the second layer is dielectrically spaced between a voltage plane and a ground plane.
6. The substrate of claim 1 , wherein the second signal traces comprise vias arranged in adjacent pairs with gaps between the adjacent pairs.
7. The substrate of claim 1 , further comprising a signal voltage power ring separated into segmented voltage supply connections laterally spaced across the upper surface and a voltage supply plane formed within the substrate, wherein the voltage supply plane is separated into segmented planes, and wherein vias electrically connect the segmented voltage supply connections to the segmented planes.
8. The substrate of claim 1 , further comprising a core voltage power ring separated into quadrants spaced across the upper surface, wherein two of the quadrants are connected to a first voltage plane, and wherein the other two quadrants are connected to a second voltage plane.
9. The substrate of claim 1 , further comprising balls formed on a lower surface of the substrate.
10. A semiconductor substrate, comprising:
signal bonding pads formed upon an upper surface of the substrate arranged in a first row and a second row, wherein an area of the upper surface is adapted to receive an integrated circuit;
first signal traces electrically connected to the first row of signal bonding pads and routed on a first layer of the substrate dielectrically spaced between a first voltage plane and a first ground plane, wherein all the first signal traces on the first layer are routed as differential pairs; and
second signal traces electrically connected to the second row of signal bonding pads and routed on a second layer of the substrate dielectrically spaced between a second voltage plane and a second ground plane.
11. The substrate of claim 10 , wherein the first layer is further spaced symmetrically between the first voltage plane and the first ground plane.
12. The substrate of claim 10 , wherein the second layer is further spaced symmetrically between the second voltage plane and the second ground plane.
13. The substrate of claim 10 , wherein all of the signal traces on the second layer are routed as differential pairs.
14. The substrate of claim 10 , wherein the first signal traces comprise blind vias extending from the upper surface to the first layer and blind vias extending from the first layer to a lower surface of the substrate.
15. The substrate of claim 10 , wherein the second signal traces comprise through hole vias extending from the upper surface to the second layer and blind vias extending from the second layer to a lower surface of the substrate.