Method of forming multiple gate insulators on a strained semiconductor heterostructure
View Patent ↗A method is disclosed for forming multiple gate insulators on a strained semiconductor heterostructure as well as the devices and circuits formed therefrom. In an embodiment, the method includes the steps of depositing a first insulators on the strained semiconductor heterostructure, removing at least a portion of the first insulators from the strained semiconductor heterostructure, and depositing a second insulators on the strained semiconductor heterostructure.
1. A method of forming multiple gate insulators, said method comprising the steps of:
providing a heterostructure comprising a strained semiconductor layer;
forming a first insulator layer having a first thickness over said heterostructure by growing an intermediate insulator layer by thermal oxidation and increasing a thickness of said intermediate insulator layer to said first thickness by deposition;
removing said first insulator layer in a region; and
forming a second insulator layer having a second thickness in said region, said second thickness being less than said first thickness; wherein a thickness of said strained semiconductor layer is substantially unchanged following the formation of said insulator layers.
2. The method as claimed in claim 1 , wherein said thickness of said intermediate insulator layer is increased to said first thickness by chemical vapor deposition.
3. The method as claimed in claim 1 , wherein said step of forming a second insulator layer comprises chemical vapor deposition.
4. The method as claimed in claim 1 , wherein said step of forming a second insulator layer comprises thermal oxidation.
5. The method as claimed in claim 1 wherein the thickness of said strained semiconductor layer is greater than approximately 50 Å.
6. The method as claimed in claim 1 , wherein said first thickness ranges from approximately 20 Å to approximately 100 Å.
7. The method as claimed in claim 1 , wherein said second thickness ranges from approximately 10 Å to approximately 20 Å.
8. The method as claimed in claim 1 , wherein a thickness of said intermediate insulator layer does not exceed approximately 10 Å.
9. A method of forming a semiconductor structure having multiple gate insulators, said method comprising the steps of:
providing a heterostructure comprising a strained semiconductor layer;
forming a plurality of insulator layers over said strained semiconductor layer, each insulator layer having a different thickness, wherein the thickness of said strained semiconductor layer is substantially unchanged following the formation of said plurality of insulator layers, the step of forming a plurality of insulator layers comprising:
forming a first insulator layer having a first thickness over said heterostructure by growing an intermediate insulator layer by thermal oxidation and increasing a thickness of said intermediate insulator layer to said first thickness by deposition; and
forming a plurality of semiconductor devices disposed over said strained semiconductor layer, each device comprising an insulator layer of said plurality of insulator layers.
10. The method as claimed in claim 9 , wherein said thickness of said intermediate insulator layer is increased to said first thickness by chemical vapor deposition.
11. The method as claimed in claim 9 , wherein the thickness of said strained semiconductor layer is greater than approximately 50 Å.
12. The method as claimed in claim 9 , wherein said first thickness ranges from approximately 20 Å to approximately 100 Å.
13. The method as claimed in claim 9 , wherein said second thickness ranges from approximately 10 Å to approximately 20 Å.
14. The method as claimed in claim 9 , wherein said method further comprises forming a third insulator having a third thickness in a third region of said strained semiconductor layer, said second thickness being greater than said third thickness.
15. The method as claimed in claim 9 , wherein the strained semiconductor layer comprises Si.
16. The method as claimed in claim 9 , wherein the thickness of said strained semiconductor layer is less than approximately 300 Å.
17. The method as claimed in claim 9 , wherein the plurality of insulator layers comprises silicon dioxide.
18. The method as claimed in claim 9 , wherein said heterostructure further comprises a relaxed semiconductor layer disposed at least partially underneath said strained semiconductor layer.
19. The method as claimed in claim 18 , wherein said relaxed semiconductor layer comprises SiGe, Ge, or GaAs.
20. The method as claimed in claim 1 , wherein the strained semiconductor layer comprises Si.
21. The method as claimed in claim 1 , wherein the thickness of said strained semiconductor layer is less than approximately 300 Å.
22. The method as claimed in claim 1 , wherein the plurality of insulator layers comprises silicon dioxide.
23. The method as claimed in claim 1 , wherein said heterostructure further comprises a relaxed semiconductor layer disposed at least partially underneath said strained semiconductor layer.
24. The method as claimed in claim 1 , wherein said relaxed semiconductor layer comprises SiGe, Ge, or GaAs.