IP Library Granted Patent US 6,930,051
Granted Patent B1
US 6,930,051 · App. 10/165,861 · Granted Aug 16, 2005

Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer

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Quick Facts
Patent No.
US 6,930,051
App. No.
10/165,861
Granted
Aug 16, 2005
Kind
B1
Abstract

New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Structures having features with different depth can be formed thereby in a single etching step.

Claims (5)

1. A method for fabrication of silicon-based microstructures, comprising the deposition and patterning of an etching delay layer on a surface of a substrate, and further comprising an etching process, the thickness and location of said etching delay layer being chosen to control the depth of features formed in the surface of the substrate after said etching delay layer is removed and the substrate is etched by said etching process.

2. The method of claim 1 , wherein said etching delay layer comprises an organic thin film.

3. The method of claim 2 , wherein said organic thin film comprises a polymer.

4. The method of claim 1 , wherein said etching delay layer comprises an inorganic thin film.

5. The method of claim 1 , wherein some of said features are formed with a depth differing from the depth of other of said features.

Assignments (1)
CHANGE OF NAME Recorded Nov 3, 2017
From: SANDIA CORPORATION
To: NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA, LLC
Reel/Frame 044779/0720 →