System and method of cross-clock domain rate matching
View Patent ↗Described are a system and method for providing an interface to synchronize data transfers across clock domains. A first pulse converter receives a request signal in a first clock domain and converts the request signal into a synchronization signal in a second clock domain. A second pulse converter receives the synchronization signal in the second clock domain from the first pulse converter and converts the synchronization signal into an acknowledgment signal in the first clock domain. The pulse converters cooperate thus to perform a self-acknowledging handshake that synchronizes writes and reads to and from a FIFO memory, thereby effectuating the transfer of data across two clock domains.
1. A controller for synchronizing transfers of data items stored in memory across clock domains, the controller comprising:
a first control module in a first clock domain;
a second control module in a second clock domain;
a plurality of synchronizers, each synchronizer being in electrical communication with the first and second control modules, each synchronizer having circuitry to provide a synchronization signal to the second control module in response to a request signal received from the first control module, to generate an acknowledgment signal from the synchronization signal, and to provide the acknowledgment signal to the first control module,
wherein the first control module maintains a record for each synchronizer indicating whether that synchronizer is presently ineligible to receive a request signal from the first control module, the first control module deeming a given synchronizer to be ineligible if the first control module has yet to receive an acknowledgment signal from that synchronizer for a request signal previously sent by the first control module to that synchronizer, the first control module selecting an eligible synchronizer when the first control module issues the request signal.
2. The controller of claim 1 , wherein the circuitry of each synchronizer comprises:
a first pulse converter receiving a request signal in the first clock domain from the first control module and converting the request signal into a synchronization signal in the second clock domain; and
a second pulse converter in electrical communication with the first pulse converter to receive the synchronization signal in the second clock domain from the first pulse converter and to convert the synchronization signal into an acknowledgment signal in the first clock domain.
3. The controller of claim 1 further comprising a register in each clock domain, each register maintaining a count of a number of data items stored in a memory.
4. The controller of claim 1 wherein one of the first and second clock domains is a write clock domain and the other of the first and second clock domains is a read clock domain.
5. The controller of claim 1 wherein each control module includes a register for maintaining a count of a number of data items stored in the memory.
6. The controller of claim 1 , wherein the first control module selects the eligible synchronizer from a plurality of eligible synchronizers in a round robin fashion.
7. The controller of claim 1 , wherein the first control module is a write control module, the second control module is a read control module, and the synchronizers are write synchronizers, and further comprising:
a plurality of read synchronizers, each read synchronizer being in electrical communication with the write and read control modules, each read synchronizer having circuitry to provide a synchronization signal to the write control module in response to a request signal received from the read control module, to generate an acknowledgment signal from this synchronization signal, and to provide this acknowledgment signal to the read control module.
8. The controller of claim 7 , wherein a number of write synchronizers and a number of read synchronizers are determined such that at least one of the write synchronizers is eligible to receive a request signal from the write control module and at least one of the read synchronizers is eligible to receive a request signal from the read control module throughout operation of the controller.
9. The controller of claim 8 , wherein the first clock domain has a different clock frequency from the second clock domain, and the number of write synchronizers and the number of read synchronizers enable data items to be written continuously to the memory and read continuously from the memory such that an average bit rate of data written to the memory matches an average bit rate of data read from the memory.
10. A method of synchronizing data transfers between a source clock domain and a destination clock domain, the method comprising:
changing a number of data items stored in memory;
issuing a first request signal by a control module to indicate the change in the number of data items stored by the memory;
propagating, by a first synchronizer, the first request signal received from the control module in the source clock domain to the destination clock domain;
converting, by the first synchronizer, the first request signal issued to the destination clock domain into an acknowledgment signal;
propagating, by the first synchronizer, the acknowledgment signal to the control module in the source clock domain to indicate that the destination clock domain received the first request signal; and
selecting a second synchronizer for propagating a second request signal from the source clock domain to the destination clock domain if the control module has yet to receive the acknowledgment signal in response to the first request signal when the control module issues the second request signal.
11. The method of claim 10 further comprising maintaining in each clock domain a count of the number of data items stored in the memory.
12. The method of claim 11 further comprising updating in the destination clock domain the count of the number of data items stored in memory in response to receiving the first request signal.
13. The method of claim 10 wherein the source clock domain operates at a different clock frequency than the destination clock domain.
14. The method of claim 10 further comprising reading in one of the source and destination clock domains a data item from the memory and writing in the other of the source and destination clock domains a data item to the memory.
15. The method of claim 10 , further comprising the steps of:
maintaining a record for each synchronizer indicating whether that synchronizer is presently ineligible to receive a request signal from the control module, the control module deeming a given synchronizer to be ineligible if the control module has yet to receive an acknowledgment signal from that synchronizer for a request signal previously sent by the control module to that synchronizer; and
wherein the step of selecting the second synchronizer includes selecting, by the control module, an eligible synchronizer when the control module issues the second request signal.
16. The method of claim 15 , wherein the step of selecting the eligible synchronizer includes selecting the eligible synchronizer in a round robin fashion from a plurality of eligible synchronizers.
17. The method of claim 15 , wherein the control module is a write control module, a second control module is a read control module, and the plurality of synchronizers include write synchronizers and read synchronizers, and further comprising the steps of:
determining a number of write synchronizers and a number of read synchronizers such that at least one of the write synchronizers is eligible to receive a request signal from the write control module and at least one of the read synchronizers is eligible to receive a request signal from the read control module at any time during operation.
18. The method of claim 17 , wherein the source clock domain operates at a different clock frequency from the destination clock domain, and the number of write synchronizers and the number of read synchronizers enable data items to be written continuously to the memory and read continuously from the memory such that an average bit rate of data written to the memory matches an average bit rate of data read from the memory.
19. A controller for synchronizing transfers of data items stored in memory across clock domains, the controller comprising:
a write control module in a first clock domain;
a read control module in a second clock domain;
a plurality of write synchronizers, each write synchronizer being in electrical communication with the write and read control modules, each write synchronizer having circuitry to provide a synchronization signal to the read control module in response to a request signal received from the write control module, to generate an acknowledgment signal from the synchronization signal, and to provide the acknowledgment signal to the write control module; and
a plurality of read synchronizers, each read synchronizer being in electrical communication with the write and read control modules, each read synchronizer having circuitry to provide a synchronization signal to the write control module in response to a request signal received from the read control module, to generate an acknowledgment signal from this synchronization signal, and to provide this acknowledgment signal to the read control module.
20. The controller of claim 19 , wherein the first clock domain has a different clock frequency from the second clock domain, and a particular number of write synchronizers and a particular number of read synchronizers are provided to enable data items to be written continuously to the memory and read continuously from the memory such that an average bit rate of data written to the memory matches an average bit rate of data read from the memory.