Method and apparatus for data hierarchy maintenance in a system for mask description
View Patent ↗A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.
1. A computer memory comprising a hierarchical correction data, such that the hierarchical correction data is combined with a hierarchical representation of an integrated circuit (IC) layout by an operation engine program performing one or more operations on a combination of the hierarchical correction data and the hierarchical representation of the IC layout, where the combination represents a modified IC layout, and at least the hierarchical correction data is generated by a hierarchy preserver program that maintains the hierarchical representation of the IC layout.
2. The machine readable medium of claim 1 , wherein the hierarchy preserver program comprises a computer program for performing optical proximity correction of the IC layout and wherein the operation engine program comprises a design rule checker for verifying that the modified IC layout conforms to a set of design rules.
3. The machine readable medium of claim 1 , wherein the hierarchical correction data includes representations of one or more structures on the modified IC layout using phase shifting masks.
4. The machine readable medium of claim 1 , wherein the hierarchical correction data comprises a plurality of delta planes.
5. The machine readable medium of claim 1 , wherein the hierarchical correction data comprises data described in a GDS-II format.
6. The machine readable medium of claim 1 , wherein the modified IC layout is an optical proximity corrected version of the IC layout.
7. The machine readable medium of claim 1 , wherein the hierarchical correction data is combined with the hierarchical representation of the IC layout using one or more arithmetic and logical operations.
8. An apparatus comprising a data processor, and hierarchical correction data stored on a computer memory, such that the hierarchical correction data is combined with a hierarchical representation of an integrated circuit (IC) layout by an operation engine program performing one or more operations on a modified IC layout represented by a combination of the hierarchical correction data and the hierarchical representation of the IC layout, where the modified IC layout corresponds to the combination, and at least the hierarchical correction data is generated by a hierarchy preserver program that maintains the hierarchical representation of the IC layout.
9. The apparatus of claim 8 , wherein the hierarchy preserver program comprises a computer program for performing optical proximity correction of the IC layout and wherein the operation engine program comprises a design rule checker for verifying that the modified IC layout conforms to a set of design rules.
10. The apparatus of claim 8 , wherein the hierarchical correction data includes representations of one or more structures on the modified IC layout using phase shifting masks.
11. The apparatus of claim 8 , wherein the hierarchical correction data comprises a plurality of delta planes.
12. The apparatus of claim 8 , wherein the hierarchical correction data comprises data is described in a GDS-II format.
13. The apparatus of claim 8 , wherein the hierarchical correction data includes optical proximity correction data for the IC layout.
14. The apparatus of claim 8 , wherein the hierarchical correction data is combined with the hierarchical representation of the IC layout using one or more arithmetic and logical operations.