Circuit configuration for the offset compensation of a signal

1. A circuit configuration for offset compensation of a digital input signal having symbols, the circuit configuration comprising:

a recursive digital filter being supplied with the digital input signal to be compensated, said recursive digital filter having at least a first time-variable filter coefficient and a second time-variable filter coefficient;

said recursive digital filter including a register device outputting symbols of a digital intermediate signal;

said recursive digital filter including a first multiplying device and a subtracting device, said first multiplying device multiplying the symbols of the digital input signal by the first time-variable filter coefficient to obtain a digital output signal having symbols, said subtracting device subtracting the symbols of the digital intermediate signal from the symbols of the digital output signal of said first multiplying device to obtain symbols of an offset-compensated digital output signal;

said recursive digital filter including a second multiplying device and an adding device, said second multiplying device multiplying the symbols of the digital intermediate signal by the second time-variable filter coefficient to obtain a digital output signal having symbols, said adding device adding the symbols of the digital output signal of said second multiplying device to the symbols of the digital input signal to generate a digital output having symbols; and

said register device receiving the symbols of the digital output signal of said adding device.

2. The circuit configuration according to claim 1 , wherein:

the first time variable filter coefficient is two raised to a power by an exponent;

the second time variable filter coefficient is two raised to a power by an exponent;

said first multiplying device is implemented as a bit-shifting device that shifts the digital input signal by a number of bit positions corresponding to the exponent of the first time variable filter coefficient; and

said second multiplying device is implemented as a bit-shifting device that shifts the digital intermediate signal by a number of bit positions corresponding to the exponent of the second time variable filter coefficient.

3. The circuit configuration according to claim 1 , wherein:

said register device is constructed in accordance with a transfer function z −R ; and

R designates an oversampling ratio of the symbols of the digital input signal.

4. The circuit configuration according to claim 1 , wherein:

the first time variable filter coefficient is 2 v and the second time variable filter coefficient is 1-2 −v ; and

v designates a time-variable integral parameter.

5. The circuit configuration according to claim 1 , wherein:

said recursive digital filter is constructed to have a transfer function

1

1

-

γ

·

1

-

z

-

R

1

-

γ

·

z

-

R

;

R is an oversampling ratio of the symbols of the digital input signal; and

γ is the second time variable filter coefficient.

6. The circuit configuration according to claim 5 , wherein the second time variable filter coefficient is 1-2 −v .

7. The circuit configuration according to claim 1 , comprising:

a control device for setting the first time variable filter coefficient and the second time variable filter coefficient in time-dependence on the digital input signal.

8. The circuit configuration according to claim 7 , wherein:

the time variable first filter coefficient is 2 v and the second time variable filter coefficient is 1-2 −v ;

v is a time-variable integral parameter;

said register device has registers;

the digital input signal is subdivided into predefined time intervals;

said control device sets the time-variable integral parameter v to a first value at a beginning of each one of the time intervals and initializes said registers of said register device with zero to, in dependence thereon, carry out offset compensation during a first phase of a corresponding one of the time intervals; and

after the first phase has been completed, said control device sets the time-variable integral parameter v to a second value that is higher than the first value, said control device forms a mean r 0 over a particular number of the symbols of the digital input signal, and said control device initializes said registers of said register device with a value equal to 2 v ·r 0 in order to perform, in dependence on the second value, the mean r 0 , and the value equal to 2 v ·r 0 , offset compensation during a second phase of the corresponding one of the time intervals.

9. The circuit configuration according to claim 8 , wherein:

the digital input signal is a communication signal; and

the first phase and the second phase are of a length of time such that preamble information contained in a respective one of the time intervals is offset-compensated by the first phase and user information of the communication signal contained in the respective one of the time intervals is offset-compensated by the second phase.

10. A method of configuring a digital receiver of a bluetooth communication system, the method which comprises:

providing the digital receiver; and

using the a circuit configuration in the digital receiver, the circuit configuration providing offset compensation of a digital input signal having symbols, the circuit configuration containing:

a recursive digital filter being supplied with the digital input signal to be compensated, the recursive digital filter having at least a first time-variable filter coefficient and a second time-variable filter coefficient;

the recursive digital filter including a register device outputting symbols of a digital intermediate signal;

the recursive digital filter including a first multiplying device and a subtracting device, the first multiplying device multiplying the symbols of the digital input signal by the first time-variable filter coefficient to obtain a digital output signal having symbols, the subtracting device subtracting the symbols of the digital intermediate signal from the symbols of the digital output signal of the first multiplying device to obtain symbols of an offset-compensated digital output signal;

the recursvie digital filter including a second multiplying device and an adding device, the second multiplying device multiplying the symbols of the digital intremediate signal by the second time-variable filter coefficient to obtain a digital output signal having symbols, the adding device adding the symbols of the digital output signal of the second multiplying device to the symbols of the digital input signal to generate a digital output having symbols; and

the register device receiving the symbols ofthe digital output signal of the adding device.