IP Library Granted Patent US 6,904,501
Granted Patent B1
US 6,904,501 · App. 10/174,391 · Granted Jun 7, 2005

Cache memory for identifying locked and least recently used storage locations

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Quick Facts
Patent No.
US 6,904,501
App. No.
10/174,391
Granted
Jun 7, 2005
Kind
B1
Abstract

A cache memory includes a plurality of data memory blocks and a code memory block. Each data memory block has a plurality of storage locations and has a particular storage location identified by a same index value. The code memory block has a plurality of code values with a particular code value being associated with the same index value. The particular code value is operable to identify which ones of the particular storage locations associated with the same index value are locked to prevent alteration of contents therein. The particular code value is also operable to identify which particular storage location has been most recently used and which particular storage location has been least recently used of the particular storage locations associated with the same index value.

Claims (31)

1. A cache memory for identifying locked and least recently used storage locations, comprising:

a plurality of data memory blocks, each data memory block having a plurality of storage locations, each data memory block having a particular storage location identified by an index value;

a code memory block, the code memory block having a plurality of code values, a particular code value being associated with the index value, the particular code value operable to identify which ones of the particular storage locations associated with the index value are locked to prevent alteration of contents therein, the particular code value operable to identify which particular storage location has been most recently used and which particular storage location has been least recently used of the particular storage locations associated with the index value;

wherein the code value is represented by five bits, the plurality of data memory blocks being a first data memory block, a second data memory block, a third data memory block, and a fourth data memory block.

2. The cache memory of claim 1 , wherein a particular storage location associated with the index value in the first data memory block is locked when a first bit and a second bit of the code value are equal to a third bit and a fourth bit of the code value.

3. The cache memory of claim 2 , wherein the particular storage locations associated with the index value of the first and second data memory blocks are locked when the first and second bits and the third and fourth bits of the code value have values of zero.

4. The cache memory of claim 3 , wherein the code value identifies the particular storage location associated with the index value of the first data memory block as being most recently used.

5. The cache memory of claim 4 , wherein the fifth bit of the code value identifies which particular storage location associated with the index value of the third and fourth data memory blocks as being least recently used.

6. The cache memory of claim 2 , wherein the code value identifies the particular storage location of the first data memory block as being most recently used.

7. The cache memory of claim 2 , wherein the first and second bits of the code value identifies which particular storage location of the second, third, and fourth data memory blocks has been least recently used.

8. The cache memory of claim 1 , wherein none of the particular storage locations associated with the index value in the first, second, third, and fourth data memory blocks are locked when a first bit and a second bit of the code value are different than a third bit and a fourth bit of the code value.

9. The cache memory of claim 8 , wherein the first and second bits of the code value identify which particular storage location associated with the index value in the first, second, third, and fourth data memory blocks has been least recently used.

10. The cache memory of claim 8 , wherein the third and fourth bits of the code value identify which particular storage location associated with the index value in the first, second, third, and fourth data memory blocks has been most recently used.

11. The cache memory of claim 8 , wherein the fifth bit of the code value identifies which particular storage location associated with the index value in the first, second, third, and fourth data memory blocks has been second most recently used and second least recently used.

12. The cache memory of claim 1 , further comprising:

a logic circuit operable to determine the code value.

13. The cache memory of claim 12 , wherein the logic circuit is operable to receive a hit signal identifying which particular storage location associated with the index value has been most recently accessed, the logic circuit operable to adjust the code value in response to the hit signal.

14. The cache memory of claim 12 , wherein the logic circuit is operable to output an indication of which particular storage location associated with the index value has been least recently used.

15. A method for identifying locked and least recently used storage locations in a cache memory, comprising:

determining an access order of a plurality of data memory blocks associated with an index from least recently used to most recently used;

determining which of the plurality of data memory blocks is to be locked and prevented from having its contents replaced;

encoding into a single code value an identity of a most recently used data memory block, a least recently used data memory block, and any locked data memory blocks;

associating the single code value with the index;

wherein the third and fourth bits of the single code value are not equal to the first and second bits of the single code value in response to none of the data memory blocks being locked.

16. A method for identifying locked and least recently used storage locations in a cache memory, comprising:

determining an access order of a plurality of data memory blocks associated with an index from least recently used to most recently used;

determining which of the plurality of data memory blocks is to be locked and prevented from having its contents replaced;

encoding into a single code value an identity of a most recently used data memory block, a least recently used data memory block, and any locked data memory blocks;

associating the single code value with the index;

wherein at least one of the data memory blocks is locked in response to the third and fourth bits of the single code value being equal to the first and second bits of the single code value.

17. The method of claim 16 , wherein the first and second bits of the single code value identify the data memory block as being least recently used.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2013
From: GRAPHICS PROPERTIES HOLDINGS, INC.
To: RPX CORPORATION
Reel/Frame 029564/0799 →
CHANGE OF NAME Recorded Aug 26, 2009
From: SILICON GRAPHICS, INC.
To: GRAPHICS PROPERTIES HOLDINGS, INC.
Reel/Frame 023134/0827 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2007
From: GENERAL ELECTRIC CAPITAL CORPORATION
To: MORGAN STANLEY & CO., INCORPORATED
Reel/Frame 019995/0895 →
SECURITY INTEREST Recorded Oct 24, 2006
From: SILICON GRAPHICS, INC.
To: GENERAL ELECTRIC CAPITAL CORPORATION
Reel/Frame 018545/0777 →
SECURITY AGREEMENT Recorded Aug 19, 2005
From: SILICON GRAPHICS, INC. AND SILICON GRAPHICS FEDERAL, INC. (EACH A DELAWARE CORPORATION)
To: WELLS FARGO FOOTHILL CAPITAL, INC.
Reel/Frame 016871/0809 →