Reduced verification complexity and power saving features in a pipelined integrated circuit
View Patent ↗An integrated circuit that uses a functional unit that outputs one set of values when in a power saving mode is provided. The functional unit, generally pipelined, is capable of being in the power saving mode dependent on an instruction decode/issue unit, and when in the power saving mode, the functional unit, using power saving mode circuitry, outputs one set of values as seen by components external to the functional unit regardless of the state the functional unit is in when the functional unit is initially put in the power saving mode.
1. An integrated circuit, comprising:
an instruction decode/issue unit that processes a plurality of instructions; and
a functional unit that inputs and executes the plurality of instructions, wherein the functional unit comprises:
a first portion that is in a power saving mode dependent on a signal generated from the instruction decode/issue unit, wherein the first portion can be in any one of a plurality of states when in the power saving mode, and
a second portion that outputs a particular value when in the power saving mode, wherein the particular value is independent of any one of the plurality of states.
2. The integrated circuit of claim 1 , wherein the functional unit is pipelined.
3. The integrated circuit of claim 1 , wherein the first portion is dependent on the signal and the clock signal when the functional unit is in a normal mode.
4. The integrated circuit of claim 1 , wherein the second portion comprises a state device that inputs the signal and is clocked by the clock signal, wherein the state device is operatively connected to a stage of the first portion.
5. The integrated circuit of claim 4 , further comprising circuitry operatively connected to the state device, wherein the circuitry outputs a particular value when the signal is at a first value, and wherein the circuitry outputs a value corresponding to the stage when the signal is at a second value.
6. A method for performing integrated circuit operations, comprising:
decoding and issuing a plurality of instructions using an instruction decode/issue unit;
generating a signal to a functional unit dependent on the decoding and issuing;
inputting and executing the plurality of instructions using a first portion of the functional unit; and
outputting a particular value from a second portion of the functional unit when the functional unit is in a power saving mode, wherein the functional unit is in the power saving mode dependent on the signal, and wherein the particular value is independent of any one of a number of states the first portion can be in when the functional unit is in the power saving mode.
7. The method of claim 6 , wherein the functional unit is pipelined.
8. The method of claim 6 , further comprising:
when in a normal mode, using a clock signal and the signal to update state of the first portion and output a set of values corresponding to a state of the first portion.
9. The method of claim 8 , further comprising:
when in the power saving mode, outputting a particular value from a state device in the second portion dependent on the signal being at a first value; and
when in the normal mode, outputting a value corresponding to a particular stage of the first portion.
10. An integrated circuit, comprising:
instruction processing means for decoding and issuing a plurality of instructions; and
instruction execution means for inputting and executing the plurality of instructions, wherein the instruction means comprises:
means for being in any one of a plurality of states when in a power saving mode, and
means for outputting a particular value when in the power saving mode, wherein the particular value is independent of any one of the plurality of states.