Semiconductor device and manufacturing thereof

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Quick Facts

Patent No.: US 7,042,055
App. No.: 10/174,948
Granted: May 9, 2006
Kind: B2

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Abstract

In a miniaturized field effect transistor, the roughness of the interface between a gate dielectric film and a gate electrode is controlled on an atomic scale. The thickness variation of the gate dielectric film is lowered, whereby a field effect transistor with high mobility is manufactured. An increase in the mobility in the field effect transistor can be achieved not only in the case of using a conventional SiO 2 thermal oxide film as the gate dielectric film but also in the case of using a high dielectric material for the gate dielectric film.

Claims (36)

1. A metal-insulator-semiconductor field effect transistor (MISFET) comprising a gate dielectric film formed from a high dielectric constant material which has a relative dielectric constant higher than that of a SiO 2 gate dielectric film and is in an amorphous state and having an equivalent oxide thickness (EOT) of silicon dioxide (t EOT ) of 2 nm or less, given by a formula t EOT =t ox ·∈ SiO2 /∈ ox , where ∈ SiO2 is a relative dielectric constant of silicon dioxide, ∈ ox is a relative dielectric constant of said gate dielectric film, and t ox is an average of the physical thickness of said gate dielectric film, wherein a ratio (Δ/t ox ) of the difference (Δ) between the maximum and the minimum of said physical thickness of said gate dielectric film present on the upper side of a channel portion of said field effect transistor to the average (t ox ) of said physical thickness is 10% or less.

2. A semiconductor device comprising a plurality of metal-insulator-semiconductor field effect transistors (MISFETS) on a semiconductor substrate, at least one of said metal-insulator-semiconductor field effect transistors (MISFETS) comprising a gate dielectric film formed from a high dielectric constant material which has a relative dielectric constant higher than that of a SiO 2 gate dielectric film and is in an amorphous state and having an equivalent oxide thickness (EOT) of silicon dioxide (t EOT ) of 2 nm or less, given by the formula t EOT =t ox·∈ SiO2 /∈ ox , where ∈ SiO2 is a relative dielectric constant of silicon dioxide, ∈ ox is a relative dielectric constant of said gate dielectric film, and t ox is an average of the physical thickness of said gate dielectric film, wherein a ratio (Δ/t ox ) of the difference (Δ) between the maximum and the minimum of said physical thickness of said gate dielectric film present on the upper side of a channel portion of said field effect transistor to the average (t ox ) of said physical thickness is 10% or less.

3. A metal-insulator-semiconductor field effect transistor (MISFET) comprising a gate dielectric film formed from a high dielectric constant material which has a relative dielectric constant higher than that of a SiO 2 gate dielectric film and is in an amorphous state and having an equivalent oxide thickness (EOT) of silicon dioxide (t EOT ) of 2 nm or less, given by a formula t EOT =t ox ·∈ SiO2 /∈ ox , where ∈ SiO2 is a relative dielectric constant of silicon dioxide, ∈ ox is a relative dielectric constant of said gate dielectric film, and t ox is an average of the physical thickness of said gate dielectric film, wherein dispersion (Δ RSR ) of said physical thickness of said gate dielectric film present on the upper side of a channel portion of said field effect transistor is 0.15·∈ ox /∈ SiO2 nm or less.

4. A semiconductor device comprising a plurality of metal-insulator-semiconductor field effect transistors (MISFETS) on a semiconductor substrate, at least one of said metal-insulator-semiconductor field effect transistors (MISFETS) comprising a gate dielectric film formed from a high dielectric constant material which has a relative dielectric constant higher than that of a SiO 2 gate dielectric film and is in an amorphous state and having an equivalent oxide thickness (EOT) of silicon dioxide (t EOT ) of 2 nm or less, given by the formula t EOT =t ox ·∈ SiO2 /∈ ox , where ∈ SiO2 is a relative dielectric constant of silicon dioxide, ∈ ox is a relative dielectric constant of said gate dielectric film, and t ox is an average of the physical thickness of said gate dielectric film, wherein dispersion (Δ RSR ) of said physical thickness of said gate dielectric film present on the upper side of a channel portion of said at least one field effect transistor is 0.15·∈ ox /∈ SiO2 nm or less.

5. A metal-insulator-semiconductor field effect transistor (MISFET) comprising a gate dielectric film formed from a high dielectric constant material which has a relative dielectric constant higher than that of a SiO 2 gate dielectric film and is in an amorphous state, wherein a value of correlation length Λ RSR of gate roughness obtained by fitting a correlation function of a physical thickness of said gate dielectric film present at a channel portion of said field effect transistor with a Gaussian distribution by the least squares method is in the range of Λ RSR <1.0 nm or Λ RSR >2.5 nm.

6. A semiconductor device comprising a plurality of metal-insulator-semiconductor field effect transistors (MISFETS) on a semiconductor substrate, at least one of said metal-insulator-semiconductor field effect transistors (MISFETS) having a gate dielectric film formed from a high dielectric constant material which has a relative dielectric constant higher than that of a SiO 2 gate dielectric film and is in an amorphous state and wherein a value of a correlation length Λ RSR of gate roughness obtained by fitting a correlation function of a physical thickness of said gate dielectric film present at a channel portion of said field effect transistor with a Gaussian distribution by the least squares method is in the range of Λ RSR <1.0 nm or Λ RSR >2.5 nm.

7. The metal-insulator-semiconductor field effect transistor (MISFET) of claim 1 , wherein electron mobility of conduction electrons in said MISFET is of an order of magnitude of hundreds of units of cm 2 /V·s.

8. The metal-insulator-semiconductor field effect transistor (MISFET) of claim 7 , wherein said electron mobility of said conduction electrons in said MISFET is less than about 400 cm 2 /V·s.

9. The semiconductor device of claim 2 , wherein electron mobility of conduction electrons in said at least one of said MISFETs is of an order of magnitude of hundreds of units of cm 2 /V·s.

10. The semiconductor device of claim 9 , wherein electron mobility of conduction electrons in said at least one of said MISFETs is less than about 400 cm 2 /V·s.

11. The metal-insulator-semiconductor field effect transistor (MISFET) of claim 3 , wherein electron mobility of conduction electrons in said MISFET is of an order of magnitude of hundreds of units of cm 2 /V·s.

12. The metal-insulator-semiconductor field effect transistor (NISFET) of claim 11 , wherein said electron mobility of said conduction electrons in said MISFET is less than about 400 cm 2 /V·s.

13. The semiconductor device of claim 4 , wherein electron mobility of conduction electrons in said at least one of said MISFETs is of an order of magnitude of hundreds of units of cm 2 /V·s.

14. The semiconductor device of claim 13 , wherein electron mobility of conduction electrons in said at least one of said MISFETs is less than about 400 cm 2 /V·s.

15. The metal-insulator-semiconductor field effect transistor (MISFET) of claim 5 , wherein electron mobility of conduction electrons in said MISFET is of an order of magnitude of hundreds of units of cm 2 /V·s.

16. The metal-insulator-semiconductor field effect transistor (MISFET) of claim 15 , wherein said electron mobility of said conduction electrons in said MISFET is less than about 400 cm 2 /V·s.

17. The semiconductor device of claim 6 , wherein electron mobility of conduction electrons in said at least one of said MISFETs is of an order of magnitude of hundreds of units of cm 2 /V·s.

18. The semiconductor device of claim 17 , wherein electron mobility of conduction electrons in said at least one of said MISFETs is less than about 400 cm 2 /V·s.

19. The metal-insulator-semiconductor field effect transistor (MISFET) of claim 1 , wherein said MISFET is devoid of a floating gate electrode, and an amorphous Si film having an average physical thickness of 8 nm or less is provided on said gate dielectric film.

20. The semiconductor device of claim 2 , wherein said at least one of said MISFETs is devoid of a floating gate electrode, and an amorphous Si film having an average physical thickness of 8 nm or less is provided on said gate dielectric film.

21. The metal-insulator-semiconductor field effect transistor (MISFET) of claim 3 , wherein said MISFET is devoid of a floating gate electrode, and an amorphous Si film having an average physical thickness of 8 nm or less is provided on said gate dielectric film.

22. The semiconductor device of claim 4 , wherein said at least one of said MISFETs is devoid of a floating gate electrode, and an amorphous Si film having an average physical thickness of 8 nm or less is provided on said gate dielectric film.

23. The metal-insulator-semiconductor field effect transistor (MISFET) of claim 5 , wherein said MISFET is devoid of a floating gate electrode, and an amorphous Si film having an average physical thickness of 8 nm or less is provided on said gate dielectric film.

24. The semiconductor device of claim 6 , wherein said at least one of said MISFETs is devoid of a floating gate electrode, and an amorphous Si film having an average physical thickness of 8 nm or less is provided on said gate dielectric film.

25. A metal-insulator-semiconductor field effect transistor (MISFET) of claim 1 ,