Pulse width communications using precision timing
Systems and methods are described for pulse communications using precision timing. A method includes digitally pulse coding a data stream; and modulating a carrier signal using the digitally pulse coded data stream.
1. A method, comprising:
pulse coding a data stream;
modulating a carrier signal using the pulse coded data stream;
digitally pulse coding a second data stream; and
phase modulating the carrier signal with the pulse coded second data stream,
characterized in that the data stream is pulse coded with a digital circuit.
2. A method, comprising:
pulse coding a data stream;
modulating a carrier signal using the pulse coded data stream;
digitally pulse coding a second data stream;
amplitude modulating the carrier signal with the second digitally pulse coded data stream;
digitally pulse coding a third data stream;
phase shifting a portion of the carrier signal;
amplitude modulating the phase shifted portion of the carrier signal; and
adding the amplitude modulated carrier signal with the amplitude modulated phased shifted portion of the carrier signal,
characterized in that the data stream is pulse coded with a digital circuit.
3. A method, comprising:
pulse coding a data stream;
modulating a carrier signal using the pulse coded data stream;
digitally pulse coding a second data stream;
phase modulating the carrier signal with the second digitally pulse coded data stream; digitally pulse coding a third data stream; and amplitude modulating the phase modulated carrier signal,
characterized in that the data stream is pulse coded with a digital circuit.
4. A method, comprising:
pulse coding a data stream;
modulating a carrier signal using the pulse coded data stream;
digitally pulse coding a second data stream;
pulse modulating a phase shifted portion of the carrier signal with the second pulse coded data stream; and
adding the pulse modulated phase shifted portion of the carrier signal to the pulse modulated carrier signal,
characterized in that the data stream is pulse coded with a digital circuit.
5. The method of claim 4 , further comprising digitally pulse coding a third data stream; amplitude modulating the carrier signal with the third pulse coded data stream; digitally pulse coding a fourth data stream; and amplitude modulating the phase shifted portion of the carrier signal with the fourth pulse coded data stream.
6. A method, comprising:
pulse coding a data stream; and
modulating a carrier signal using the pulse coded data stream, characterized in that the data stream is pulse coded with a digital circuit, wherein the carrier signal is modulated with a precision that is sub clock cycle with regard to a clock that is controlling the digital circuit that is pulse coding the data stream;
digitally pulse coding a second data stream; and
phase modulating the carrier signal with the pulse coded second data stream.
7. A method, comprising:
pulse coding a data stream; and
modulating a carrier signal using the pulse coded data stream, characterized in that the data stream is pulse coded with a digital circuit, wherein the carrier signal is modulated with a precision that is sub clock cycle with regard to a clock that is controlling the digital circuit that is pulse coding the data stream;
digitally pulse coding a second data stream; amplitude modulating the carrier signal with the second digitally pulse coded data stream;
digitally pulse coding a third data stream; phase shifting a portion of the carrier signal;
amplitude modulating the phase shifted portion of the carrier signal; and
adding the amplitude modulated carrier signal with the amplitude modulated phased shifted portion of the carrier signal.
8. A method, comprising:
pulse coding a data stream; and
modulating a carrier signal using the pulse coded data stream, characterized in that the data stream is pulse coded with a digital circuit, wherein the carrier signal is modulated with a precision that is sub clock cycle with regard to a clock that is controlling the digital circuit that is pulse coding the data stream;
digitally pulse coding a second data stream;
phase modulating the carrier signal with the second digitally pulse coded data stream;
digitally pulse coding a third data stream; and
amplitude modulating the phase modulated carrier signal.
9. A method, comprising:
pulse coding a data stream; and
modulating a carrier signal using the pulse coded data stream, characterized in that the data stream is pulse coded with a digital circuit, wherein the carrier signal is modulated with a precision that is sub clock cycle with regard to a clock that is controlling the digital circuit that is pulse coding the data stream;
digitally pulse coding a second data stream; pulse modulating a phase shifted portion of the carrier signal with the second pulse coded data stream; and
adding the pulse modulated phase shifted portion of the carrier signal to the pulse modulated carrier signal.
10. The method of claim 9 , further comprising digitally pulse coding a third data stream; amplitude modulating the carrier signal with the third pulse coded data stream; digitally pulse coding a fourth data stream; and amplitude modulating the phase shifted portion of the carrier signal with the fourth pulse coded data stream.
11. An apparatus, comprising:
a buffer;
a pulse generator coupled to the buffer;
a modulator coupled to the pulse generator;
an oscillator coupled to the modulator;
a decoder coupled to the buffer;
another buffer coupled to the decoder; and
a sub clock cycle pulse generator coupled between the another buffer and the pulse generator,
characterized in that the buffer and the pulse generator define a digital circuit.
12. The apparatus of claim 11 , further comprising an integrator coupled to the sub clock cycle pulse generator; a sample and hold circuit coupled to the integrator; and a phase shifter coupled a) between the sample and hold circuit and the modulator and b) between the oscillator and the modulator.
13. The apparatus of claim 11 , further comprising an integrator coupled to the sub clock cycle pulse generator; a sample and hold circuit coupled to the integrator; and another modulator coupled a) between the sample and hold circuit and the modulator and b) between the oscillator and the modulator.
14. An apparatus, comprising:
a buffer;
a pulse generator coupled to the buffer;
a modulator coupled to the pulse generator;
an oscillator coupled to the modulator; a decoder coupled to the buffer; a k-bit buffer coupled to the decoder, a sub-cycle pulse generator coupled to the k-bit buffer; an integrator coupled to the sub-cycle pulse generator; a sample and hold circuit coupled to the sub-cycle pulse generator; a non-phase shifted mixer coupled to the sample and hold circuit; an adder coupled to the non-phase shifted mixer, the adder coupled to the mixer; another k-bit buffer coupled to the decoder; another sub-cycle pulse generator coupled to the another k-bit buffer; another integrator coupled to the another sub-cycle pulse generator; another sample and hold circuit coupled to the another integrator; a phase shifted modulator coupled to the another sample and hold circuit, the phase shifted mixer coupled to the adder; and a phase shifter coupled between the oscillator and the phase shifted modulator,
characterized in that the buffer and the pulse generator define a digital circuit.
15. An apparatus, comprising:
a buffer;
a pulse generator coupled to the buffer;
a modulator coupled to the pulse generator;
an oscillator coupled to the modulator;
a decoder coupled to the buffer; a p-bit buffer coupled to the decoder, a sub-cycle pulse generator coupled to the p-bit buffer; an integrator coupled to the sub-cycle pulse generator; a sample and hold circuit coupled to the sub-cycle pulse generator; another mixer coupled between the sample and hold circuit and the mixer; a q-bit buffer coupled to the decoder; another sub-cycle pulse generator coupled to the another q-bit buffer; another integrator coupled to the another sub-cycle pulse generator; another sample and hold circuit coupled to the another integrator; and a phase shifter coupled between the another sample and hold circuit and the another modulator,
characterized in that the buffer and the pulse generator define a digital circuit.
16. An apparatus, comprising:
a buffer;
a pulse generator coupled to the buffer;
a modulator coupled to the pulse generator;
an oscillator coupled to the modulator;
a decoder coupled to the buffer; another buffer coupled to the decoder, a sub-cycle pulse generator coupled to the another buffer; another modulator coupled to the sub-cycle pulse generator; an adder coupled between the modulator and the another modulator; and a phase shifter coupled between the oscillator and the another modulator,
characterized in that the buffer and the pulse generator define a digital circuit.
17. The apparatus of claim 16 , further comprising a first k-bit buffer coupled to the decoder, a second sub-cycle pulse generator coupled to the first k-bit buffer; a first integrator coupled to the second sub-cycle pulse generator; a first sample and hold circuit coupled to the first integrator, the first sample and hold circuit coupled to the modulator, a second k-bit buffer coupled to the decoder; a third sub-cycle pulse generator coupled to the second k-bit buffer; a second integrator coupled to the third sub-cycle pulse generator; and a second sample and hold circuit coupled to the second integrator, the second sample and hold circuit coupled to the another modulator.
18. An apparatus, comprising:
a buffer;
a pulse generator coupled to the buffer;
a modulator coupled to the pulse generator;
an oscillator coupled to the modulator, characterized in that the buffer and the pulse generator define a digital circuit, wherein the pulse generator provides sub clock cycle precision with regard to a clock that is controlling the digital pulse generator;
a decoder coupled to the buffer;
another buffer coupled to the decoder; and
a sub clock cycle pulse generator coupled between the another buffer and the pulse generator.
19. The apparatus of claim 18 , further comprising an integrator coupled to the sub clock cycle pulse generator; a sample and hold circuit coupled to the integrator; and a phase shifter coupled a) between the sample and hold circuit and the modulator and b) between the oscillator and the modulator.
20. The apparatus of claim 18 , further comprising an integrator coupled to the sub clock cycle pulse generator; a sample and hold circuit coupled to the integrator; and another modulator coupled a) between the sample and hold circuit and the modulator and b) between the oscillator and the modulator.
21. An apparatus, comprising:
a buffer;
a pulse generator coupled to the buffer;
a modulator coupled to the pulse generator;
an oscillator coupled to the modulator, characterized in that the buffer and the pulse generator define a digital circuit, wherein the pulse generator provides sub clock cycle precision with regard to a clock that is controlling the digital pulse generator;
a decoder coupled to the buffer;
a k-bit buffer coupled to the decoder,
a sub-cycle pulse generator coupled to the k-bit buffer;
an integrator coupled to the sub-cycle pulse generator;
a sample and hold circuit coupled to the sub-cycle pulse generator;
a non-phase shifted mixer coupled to the sample and hold circuit;
an adder coupled to the non-phase shifted mixer, the adder coupled to the mixer;
another k-bit buffer coupled to the decoder;
another sub-cycle pulse generator coupled to the another k-bit buffer;
another integrator coupled to the another sub-cycle pulse generator;
another sample and hold circuit coupled to the another integrator;
a phase shifted modulator coupled to the another sample and hold circuit, the phase shifted mixer coupled to the adder; and
a phase shifter coupled between the oscillator and the phase shifted modulator.
22. An apparatus comprising:
a buffer;
a pulse generator coupled to the buffer;
a modulator coupled to the pulse generator; and
an oscillator coupled to the modulator, characterized in that the buffer and the pulse generator define a digital circuit, wherein the pulse generator provides sub clock cycle precision with regard to a clock that is controlling the digital pulse generator;
a decoder coupled to the buffer;
a p-bit buffer coupled to the decoder;
a sub-cycle pulse generator coupled to the p-bit buffer;
an integrator coupled to the sub-cycle pulse generator;
a sample and hold circuit coupled to the sub-cycle pulse generator;
another mixer coupled between the sample and hold circuit and the mixer;
a q-bit buffer coupled to the decoder;
another sub-cycle pulse generator coupled to the another q-bit buffer;
another integrator coupled to the another sub-cycle pulse generator;
another sample and hold circuit coupled to the another integrator; and
a phase shifter coupled between the another sample and hold circuit and the another modulator.
23. An apparatus, comprising:
a buffer;
a pulse generator coupled to the buffer;
a modulator coupled to the pulse generator; and
an oscillator coupled to the modulator, characterized in that the buffer and the pulse generator define a digital circuit, wherein the pulse generator provides sub clock cycle precision with regard to a clock that is controlling the digital pulse generator;
a decoder coupled to the buffer;
another buffer coupled to the decoder;
a sub-cycle pulse generator coupled to the another buffer;
another modulator coupled to the sub-cycle pulse generator;
an adder coupled between the modulator and the another modulator; and
a phase shifter coupled between the oscillator and the another modulator.
24. The apparatus of claim 23 , further comprising a first k-bit buffer coupled to the decoder, a second sub-cycle pulse generator coupled to the first k-bit buffer; a first integrator coupled to the second sub-cycle pulse generator; a first sample and hold circuit coupled to the first integrator, the first sample and hold circuit coupled to the modulator, a second k-bit buffer coupled to the decoder; a third sub-cycle pulse generator coupled to the second k-bit buffer; a second integrator coupled to the third sub-cycle pulse generator; and a second sample and hold circuit coupled to the second integrator, the second sample and hold circuit coupled to the another modulator.