IP Library Granted Patent US 6,905,906
Granted Patent B2
US 6,905,906 · App. 10/176,007 · Granted Jun 14, 2005

Solution processed devices

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,905,906
App. No.
10/176,007
Granted
Jun 14, 2005
Kind
B2
Abstract

A method for forming a transistor, comprising: depositing a first material from solution in a first solvent to form a first layer of the transistor, and subsequently whilst the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material a second material from solution in a second solvent in which the first material is substantially insoluble.

Claims (78)

1. A method for forming a transistor, comprising:

depositing a first material from solution in a first solvent to form a first layer of the transistor; and subsequently

whilst the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material a second material from solution in a second solvent in which the first material is substantially insoluble;

wherein at least one of the first and second layers forms (i) a gate, drain or source electrode; (ii) a semiconductor layer; or (iii) an insulator layer of the transistor.

2. A method as claimed in claim 1 , comprising the further step of, whilst the second material remains soluble in the second solvent, forming a third layer of the transistor by depositing over the second material a third material from solution in a third solvent in which the second material is substantially insoluble.

3. A method as claimed in claim 1 , wherein one of the first and second solvents is a polar solvent and the other of the first and second solvents is a non-polar solvent.

4. A method as in claim 1 , wherein one of the first or second materials is a semiconductive material, and the other of the first or second materials is a dielectric material.

5. A method as in claim 2 , wherein the second material is a dielectric material, one of the first and third materials is a semiconductive material and the other of the first or third materials is a conductive material.

6. A method as claimed in claim 1 , wherein one of the first and second layers is a non-polar polymer layer that is soluble in a non-polar solvent and the other of the first and second layers is a polar polymer layer that is soluble in a polar solvent.

7. A method as claimed in claim 6 , wherein the interaction parameter D for the non-polar polymer and the polar solvent is larger than 5.

8. A method as claimed in claim 6 , wherein the interaction parameter D for the non-polar polymer and the polar solvent is larger than 10.

9. A method as claimed in claim 6 , wherein the interaction parameter D for the non-polar polymer and the polar solvent is larger than 15.

10. A method as claimed in claim 6 , wherein the interaction parameter D for the polar polymer and the non-polar solvent is larger than 5.

11. A method as claimed in claim 6 , wherein the interaction parameter D for the polar polymer and the non-polar solvent is larger than 10.

12. A method as claimed in claim 6 , wherein the interaction parameter D for the polar polymer and the non-polar solvent is larger than 15.

13. A method as claimed in claim 3 , wherein one of the second and third solvents is a polar solvent and the other of the second and third solvents is a non-polar solvent.

14. A method as claimed in claim 2 , wherein the second solvent is a moderately polar solvent containing a polar and a non-polar group and one of the first and third solvents is a highly polar solvent containing only polar groups.

15. A method as claimed in claim 14 , wherein the second polymer layer is a moderately polar polymer layer soluble in a moderately polar solvent, and one of the first or third polymer layers is a non-polar polymer layer, and the other of the first or third polymer layers is polar polymer layer.

16. A method as claimed in claim 14 wherein the interaction parameter D for the non-polar polymer and the moderately polar solvent is larger than 5.

17. A method as claimed in claim 14 wherein the interaction parameter D for the non-polar polymer and the moderately polar solvent is larger than 10.

18. A method as claimed in claim 14 wherein the interaction parameter D for the non-polar polymer and the moderately polar solvent is larger than 15.

19. A method as claimed in claim 14 wherein the interaction parameter D for the polar polymer and the moderately polar solvent is larger than 5.

20. A method as claimed in claim 14 wherein the interaction parameter D for the polar polymer and the moderately polar solvent is larger than 10.

21. A method as claimed in claim 14 wherein the interaction parameter D for the polar polymer and the moderately polar solvent is larger than 15.

22. A method as claimed in claim 14 , wherein the moderately polar solvent is an alcohol.

23. A method as claimed in claim 14 , wherein the moderately polar solvent is an acetate.

24. A method as claimed in claim 2 , wherein the first layer is soluble in a non-polar solvent and the second layer is an isolation layer soluble in a moderately polar solvent containing a hydrophilic and a hydrophobic group.

25. A method as claimed in claim 24 , wherein the third layer is soluble in a polar solvent.

26. A method as claimed in claim 24 , wherein the third layer is soluble in a non-polar solvent.

27. A method as claimed in claim 24 , wherein the second layer is an active layer of the transistor.

28. A method as claimed in claim 1 , wherein one of the first and second layers is a source and/or drain electrode layer of the transistor and the other of the first and second layers is a semiconductor layer of the transistor.

29. A method as claimed in claim 1 , wherein one of the first and second layers is a semiconductor layer of the transistor and the other of the first and second layers is an insulator layer of the transistor.

30. A method as claimed in claim 28 , wherein the semiconductor layer comprises a conjugated polymer.

31. A method as claimed in claim 28 , wherein the semiconductor layer comprises a conjugated block copolymer.

32. A method as claimed in claim 28 , wherein the semiconductor layer comprises a block copolymer comprising a first block of conjugated monomer units each linked by at least two covalent bonds, and a second block of monomer units, the block copolymer having an electron affinity greater than 3.0 eV or 3.5 eV.

33. A method as claimed in claim 28 , wherein the semiconductor layer comprises a block copolymer comprising a first block of conjugated monomer units each linked by at least two covalent bonds, and a second block of monomer units, the block copolymer having an ionisation potential in the range from 5.5 eV to 4.9 eV.

34. A method as claimed in claim 33 , wherein the first block of monomer units comprises one or more of the group comprising a fluorene derivative, a phenylene derivative and an indenofluorene derivative and the second block of monomer units comprises one or more of the group comprising a thiophene derivative, a triarylamine derivative and a benzothiadiazole derivative.

35. A method as claimed in claim 28 , wherein the semiconductor layer is F8T2 or TFB.

36. A method as claimed in claim 28 , wherein the semiconductor layer comprises a liquid-crystalline conjugated polymer.

37. A method as claimed in claim 36 , comprising the step of heating the liquid-crystalline polymer into its liquid crystalline phase.

38. A method as claimed in claim 36 , comprising the step of aligning the liquid-crystalline polymer uniaxially.

39. A method as claimed in claim 38 , wherein the step of aligning the liquid-crystal polymer comprises depositing the liquid-crystalline polymer on to a layer having an aligned molecular structure.

40. A method as claimed in claim 39 , comprising the step of aligning the molecular structure of the said layer by mechanically rubbing the layer.

41. A method as claimed in claim 39 , comprising the step of aligning the molecular structure of the said layer by optically treating the layer.

42. A method as claimed in claim 28 , wherein the semiconductor layer is optically transparent with a band gap larger than 2.3 eV, preferably larger than 2.5 eV.

43. A method as claimed in claim 28 , wherein the semiconductor layer has an ionisation potential larger than 4.9 eV.

44. A method as claimed in claim 28 , wherein the semiconductor layer has an ionisation potential larger than 5.1 eV.

45. A method as claimed in claim 28 , wherein the semiconductor layer has an electron affinity larger than 3.0 eV.

46. A method as claimed in claim 28 , wherein the semiconductor layer has an electron affinity larger than 3.5 eV.

47. A method as claimed in claim 1 , wherein one of the first and second layers is an insulator layer of the transistor and the other of the first and second layers is a gate electrode layer of the transistor.

48. A method as claimed in claim 2 , wherein one of the first and third layers is an insulator layer of the transistor, the other of the first and third layers is a gate electrode layer of the transistor, and the second layer is an isolation layer of the transistor.

49. A method as claimed in claim 48 , wherein the isolation layer is a diffusion barrier layer.

50. A method as claimed in claim 49 , wherein the diffusion barrier layer comprises a non-polar polymer.

51. A method as claimed in claim 49 , wherein the diffusion barrier layer comprises a non-polar conjugated polymer.

52. A method as claimed in claim 49 , wherein the diffusion barrier layer comprises a polyfluorene derivative.

53. A method as claimed in claim 52 , wherein the polyfluorene derivative is F8, F8T2 or TFB.

54. A method as claimed in claim 48 , wherein the isolation layer is a surface modification layer.

55. A method as claimed in claim 1 , comprising the step of modifying the surface of the first layer prior to depositing the second layer.

56. A method as claimed in claim 55 , wherein the surface modification of the first layer is such as to provide a contact angle of less than 100° for deposition of the second material onto the first layer.

57. A method as claimed in claim 55 , wherein the surface modification of the first layer is such as to provide a contact angle of less than 80° for deposition of the second material onto the first layer.

58. A method as claimed in claim 55 , wherein the surface modification of the first layer is such as to provide a contact angle of less than 60° for deposition of the second material onto the first layer.

59. A method as claimed in claim 55 , wherein the step of modifying the surface of the first layer comprises treating the surface of the first layer.

60. A method as claimed in claim 55 , wherein the step of modifying the surface of the first layer comprises depositing a surface modifying material on to the surface of the first layer.

61. A method as claimed in claim 60 , wherein the surface modifying material is deposited from solution in a moderately polar solvent.

62. A method as claimed in claim 2 , wherein the first layer is deposited on to a substrate, and the method comprises heating the substrate prior to deposition of the second or third layer.

63. A method as claimed in claim 2 , wherein at least one of the first, second and third layers is formed by ink-jet printing.

64. A method as claimed in claim 63 , wherein at least one of the source, drain or gate electrode of the transistor is formed by ink-jet printing.

65. A method as claimed in claim 1 , wherein the transistor has a source, drain or gate electrode formed of a conducting polymer.

66. A method as claimed in claim 65 , wherein the said electrode is formed of an optically transparent conducting polymer.

67. A method as claimed in claim 65 , wherein the conducting polymer contains a polymeric counterion dopant.

68. A method as claimed in claim 1 , wherein the material of one of the first and second layers is PEDOT/PSS.

69. A method as claimed in claim 1 , wherein the transistor has an insulator layer formed of a non-conjugated or partially conjugated polymer.

70. A method as claimed in claim 69 , wherein the insulating polymer contains both hydrophilic and hydrophobic groups and is soluble in a moderately polar solvent.

71. A method as claimed in claim 1 , wherein the material of one of the first and second layers is PVP.

72. A method as claimed in claim 1 , wherein the first and second layers form different ones of (i) a gate, drains or source electrode, (ii) a semiconductor layer, and (iii) an insulator layer of the transistor.

73. A method for forming a transistor, comprising:

depositing a first material from solution in a first solvent to form a first layer of the transistor; and subsequently

whilst the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material a second material from solution in a second solvent in which the first material is substantially insoluble; wherein the first layer is an insoluble layer or semiconductor layer of the transistor.

Assignments (3)
CHANGE OF NAME Recorded May 5, 2016
From: PLASTIC LOGIC LIMITED
To: FLEXENABLE LIMITED
Reel/Frame 038617/0662 →
RELEASE OF SECURITY INTEREST Recorded May 12, 2011
From: STATE CORPORATION "RUSSIAN CORPORATION OF NANOTECHNOLOGIES"
To: PLASTIC LOGIC LIMITED
Reel/Frame 026271/0377 →
SECURITY AGREEMENT Recorded Aug 3, 2010
From: PLASTIC LOGIC LIMITED
To: STATE CORPORATION "RUSSIAN CORPORATION OF NANOTECHNOLOGIES"
Reel/Frame 024776/0357 →