Substrate configurable JTAG ID scheme
View Patent ↗A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port circuit may be configured to determine an identification value in response to the signal.
1. An apparatus comprising:
a chip having (i) a core circuit configurable among a plurality of functions in response to a signal and (ii) a test access port circuit configured to determine an identification value in response to said signal, wherein said signal has a width of at least one bit;
a package (i) enclosing said chip, (ii) having at least one signal trace configured to carry said at least one bit of said signal respectively, (iii) a plurality of reference traces each having a unique value and (iv) at least one jumper coupling a respective one of said at least one signal trace to one of said reference traces; and
another chip having another test access port circuit (i) interfacing with another core circuit and (ii) configured to suppress another identification value in response to said signal.
2. The apparatus according to claim 1 , further comprising a circuit board configured to bias said reference traces to generate said at least one bit of said signal.
3. The apparatus according to claim 2 , further comprising a plurality of interfaces on said circuit board each having one of said unique values, wherein one of said interfaces is connected to said at least one signal trace.
4. The apparatus according to claim 1 , wherein said at least one bit comprises a plurality of bits, said apparatus further comprising a bond connecting a second bit of said plurality of bits directly to one of said reference traces.
5. A method of operating a circuit, comprising the steps of:
(A) receiving a signal;
(B) configuring a chip of said circuit among a plurality of functions in response to said signal;
(C) determining a test access port identification value for said chip in response to said signal, said test access port identification value comprising a plurality of digital bits;
(D) generating said signal external to said chip; and
(E) suppressing another test access port identification value for another chip of said circuit in response to said signal.
6. The method according to claim 5 , further comprising the step of generating a plurality of values for said signal external to said chip, wherein one of said values is received by said chip.
7. An apparatus comprising:
a chip having (A) a core circuit configurable among a plurality of functions in response to a signal, B a test access port circuit configured to determine an identification value in response to said signal and (C) a bond connecting said chip to one of a plurality of traces each (i) carrying a unique value for said signal and (ii) external to said chip; and
another chip having another test access port circuit (A) interfacing with another core circuit and (B) configured to suppress another identification value in response to said signal.
8. The apparatus according to claim 7 , wherein a memory circuit enclosed in a common package with said chip is configured to generate said signal.
9. The apparatus according to claim 8 , wherein said memory circuit comprises an optical memory circuit.
10. The apparatus according to claim 8 , wherein said memory circuit comprises a magnetic memory circuit.
11. The apparatus according to claim 7 , wherein a fuse programmable link is configured to generate said signal.
12. The apparatus according to claim 7 , wherein an antifuse programmable link is configured to generate said signal.
13. The apparatus according to claim 7 , wherein said identification value comprises a Joint Test Action Group product identification value.
14. An apparatus comprising:
a first core circuit configurable among a plurality of functions in response to a signal having a multi-bit width;
a first test access port circuit configured to determine a first identification value in response to said signal;
a second core circuit;
a second test access port circuit (i) interfacing with said second core circuit and (ii) configured to suppress a second identification value in response to said signal;
a package (i) enclosing said first core circuit, said second core circuit, said first test access port and said second test access port and (ii) having a plurality of signal traces configured to carry said signal; and
a plurality of jumpers in said package coupling said signal traces to a plurality of reference traces to generate a unique value for said signal.
15. The apparatus according to claim 14 , wherein said reference traces comprises:
a high reference trace carrying a high voltage; and
a low reference trace carrying a low voltage.
16. The apparatus according to claim 14 , wherein said jumpers comprise a plurality of wire bonds.
17. The apparatus according to claim 14 , wherein each of said jumpers comprise a trace between a respective one of said signal traces and one of said reference traces.
18. A method of operating a circuit, comprising the steps of:
(A) receiving a signal;
(B) configuring a chip of said circuit among a plurality of functions in response to said signal;
(C) determining a test access port identification value for said chip in response to said signal, said test access port identification value comprising a plurality of digital bits;
(D) generating said signal external to said chip; and
(E) generating a plurality of values for said signal external to said chip, wherein only one of said values is received by said chip.
19. The method according to claim 18 , further comprising the step of suppressing another test access port identification value for another chip of said circuit in response to said signal.