Calculating circuit and method for computing an
View Patent ↗A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an integrator circuit, and a multiplier circuit. The subtractor circuit responsive to a first signal and a feedback signal and configured for generating an error signal representing a difference between the first signal and the feedback signal. The integrator circuit responsive to the error signal and configured for computing the output signal. The multiplier circuit responsive to the output signal and configured for generating a feedback signal. The method for generating the output signal includes the following iterative steps: (i) generating an error signal at a j-th iteration, (ii) integrating the error signal for obtaining the output signal, (iii) generating the feedback signal and (iv) repeating steps (i) to (iii) as required to obtain the N-th root and reciprocal with a required accuracy.
1. A calculating circuit for generating an output signal representing an output number approximating an N-th root or a reciprocal of an input number represented by an input signal, the calculating circuit comprising:
a subtractor circuit responsive to a first signal and a feedback signal and configured for generating an error signal representing a difference between said first signal and said feedback signal;
an integrator circuit responsive to said error signal and configured for computing said output signal;
a multiplier circuit responsive to said output signal and configured for generating said feedback signal.
2. The calculating circuit of claim 1 wherein said first signal is said input signal.
3. The calculating circuit of claim 1 wherein said first signal is a reference signal.
4. The calculating circuit of claim 3 wherein said reference signal is represented by a constant value equal to 1.
5. The calculating circuit of claim 1 wherein said feedback signal is equal in magnitude to a product of said output signal and said input signal.
6. The calculating circuit of claim 1 wherein said feedback signal is equal in magnitude to said output signal raised to the power N.
7. The calculating circuit of claim 1 wherein said input signal is selected from direct current signal and alternating current signal.
8. The calculating circuit of claim 1 wherein said subtractor circuit is implemented as a module from the list including differential amplifier, digital subtractor and a part of processor operation.
9. The calculating circuit of claim 8 wherein the processor is selected from: microprocessor, microcontroller and digital signal processor (DSP).
10. The calculating circuit of claim 1 wherein said integrator circuit is selected from digital circuit, analog circuit and part of processor operation.
11. The calculating circuit of claim 10 wherein the processor is selected from: microprocessor, microcontroller and digital signal processor (DSP).
12. The calculating circuit of claim 1 wherein said integrator circuit is selected from digital circuit, analog circuit and part of processor operation.
13. The calculating circuit of claim 12 wherein the processor is selected from: microprocessor, microcontroller and digital signal processor (DSP).
14. The calculating circuit of claim 1 wherein said integrator circuit is configured to compute said output signal in successive iterations according to the equation: Z out (j)=Z out (j−1)+K·E s (j), wherein Z out (j) is a value of the output signal at the j-th iteration, E s (j) is the error signal at the j-th iteration, and K is a gain factor.
15. The calculating circuit of claim 14 wherein said gain factor K is set to optimize between a number of iterations necessary for convergence and a number of iterations necessary to maintain stability of the feedback signal.
16. The calculating circuit of claim 14 wherein an appropriate value of said gain factor K is chosen to be a function of the input signal level.
17. The calculating circuit of claim 14 wherein a value of said gain factor K approximately equals to 2/Z 1in .
18. The calculating circuit of claim 14 wherein a value of said gain factor K is less than 2/Z in .
19. A calculating circuit for generating an output signal representing an output number approximating an N-th root of an input number represented by an input signal, the calculating circuit comprising:
a subtractor circuit responsive to said input signal and configured for generating an error signal representing a difference between said input signal and a feedback signal representing the output signal raised to the power N;
an integrator circuit responsive to said error signal and configured for computing said output signal; and
a multiplier circuit responsive to said output signal and configured for generating the feedback signal.
20. The calculating circuit of claim 19 wherein said integrator circuit is configured to compute said output signal in successive iterations according to the equation: Z out (j)=Z out (j−1)+K·E s (j), wherein Z out (j) is a value of the output signal at the j-th iteration, E s (j) is the error signal at the j-th iteration, and K is a gain factor.
21. The calculating circuit of claim 20 wherein said gain factor K is set to optimize between a number of iterations necessary for convergence and a number of iterations necessary to maintain stability of the feedback signal.
22. The calculating circuit of claim 20 wherein an appropriate value of said gain factor K is chosen to be a function of the input signal level.
23. The calculating circuit of claim 20 wherein a value of said gain factor K approximately equals to 2/Z in .
24. The calculating circuit of claim 20 wherein a value of said gain factor K is less than 2/Z in .
25. A calculating circuit for generating an output signal representing an output number approximating a reciprocal of an input number represented by an input signal, the calculating circuit comprising:
a subtractor circuit responsive to said input signal for generating an error signal representing a difference between a reference signal and a feedback signal representing a product of an output signal and said input signal;
an integrator circuit responsive to said error signal for generating said output signal; and
a multiplier circuit responsive to said output signal and to said input signal for generating said feedback signal.
26. The calculating circuit of claim 25 wherein wherein said integrator circuit is configured to compute said output signal in successive iterations according equation: Z out (j)=Z out (j−1)+K·E s (j), wherein Z out (j) is a value of the output signal at the j-th iteration, E s (j) is the error signal at the j-th iteration, and K is a gain factor.
27. The calculating circuit of claim 26 wherein said gain factor K is set to optimize between a number of iterations necessary for convergence and a number of iterations necessary to maintain stability of the feedback signal.
28. The calculating circuit of claim 26 wherein a value of the gain factor K is selected from the range of 0 to ½.