IP Library Granted Patent US 7,242,719
Granted Patent B2
US 7,242,719 · App. 10/182,158 · Granted Jul 10, 2007

Method and apparatus for space-saving-variable length encoding and decoding

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Quick Facts
Patent No.
US 7,242,719
App. No.
10/182,158
Granted
Jul 10, 2007
Kind
B2
Abstract

A sequence of input information items is space-saving-encoded into variable-length code bit groups. Each information item is mapped on an associated code bit group of a set of bit groups, wherein the bit groups have particular lengths that are non-uniform in the set. The code bit groups are chained into a chaining configuration of bit groups while allowing progressive delimiting of successive bit groups. For regressive delimiting of successive bit groups, each bit group as divided into an idiosyncratic sequence of subgroups. In each sequence, the subgroups are assigned to a respective sub-chainings. The sub-chainings are configured into respective sub-chaining configurations, while maintaining pointer information regarding each respective sub-chaining configuration to preserve mutual synchronization among the various sub-chaining configurations regarding the associated in formation items.

Claims (28)

1. An encoding method for space-saving-encoding of a sequence of input information items, said method comprising the acts of:

mapping each information item on an associated code bit group of a set of variable-length code bit groups;

chaining said code bit groups into a chaining configuration of code bit groups whilst providing means for allowing progressive delimiting of successive code bit groups;

allowing regressive delimiting of successive code bit groups through dividing each code bit group into a sequence of code bit subgroups and in each sequence assigning the code bit subgroups to respective sub-chainings; and

configuring the sub-chainings into respective sub-chaining configurations, whilst maintaining pointer informations regarding each respective sub-chaining configuration to preserve mutual synchronization among the various sub-chaining configurations regarding the associated information items.

2. The method as claimed in claim 1 , wherein at least one code bit subgroup consists of a single bit.

3. The method as claimed in claim 1 , wherein all code bit subgroups consist of a single bit.

4. The method as claimed in claim 1 , wherein each code bit group uniformly has at least one bit assigned to a particular sub-chaining of code bit subgroups.

5. The method as claimed in claim 2 , wherein regarding to a single information item a next subgroup of its code bit group has no higher number of bits than a preceding one.

6. The method as claimed in claim 1 , wherein the method is applied to an embedded system that has a textual interface, or is applied to a processor instruction set, or is applied to data subject to interpretation, or is applied to an audio/video signal.

7. The method as claimed in claim 1 , further comprising the act of storing or transmitting data so encoded, and thereto joining a set of said pointer informations.

8. An encoding apparatus being arranged for space-saving-encoding of a sequence of input information items said apparatus comprising:

mapping means for mapping each information item on an associated code bit group of a set of variable length code bit groups,

chaining means for chaining said code bit groups into a chaining configuration whilst providing means for allowing progressive delimiting of successive code bit groups,

means for allowing regressive delimiting of successive code bit groups comprising dividing means for regressive delimiting successive code bit groups by dividing each bit group into an sequence of subgroups;

assigning means for in each sequence assigning the subgroups to respective sub-chainings;

and configuring means for configuring the sub-chainings into respective sub-chaining configurations, whilst maintaining pointer informations for each respective sub-chaining configuration to preserve mutual synchronization among the various sub-chaining configurations regarding the associated information items.

9. The apparatus as claimed in claim 8 , wherein at least one code bit subgroup consists of a single bit.

10. The apparatus as claimed in claim 8 , wherein each code bit group uniformly has at least one bit assigned to a particular sub-chaining of code bit subgroups.

11. The apparatus as claimed in claim 8 , further comprising means for storing or transmitting data so encoded, and thereto joining a set of said pointer informations.

12. An apparatus being arranged for regressive decoding of a space-saving chaining configuration encoded, said apparatus comprising:

receiving means for receiving a pointer to said chaining configuration;

delimiting means for delimiting a particular code bit group;

and decoding means for decoding a delimited code bit group into an associated information item for outputting,

said delimiting means comprising:

primary access means for accessing a first pointer information associated to a first sub-chaining configuration;

secondary access means fed by said first pointer information and by a code bit sub-group of said first sub-chaining configuration for recursively accessing any other sub-chaining configuration on the basis of an earlier pointer information and a code bit sub-group of an earlier sub-chaining configuration for so reconstituting an associated code bit group for forwarding to said decoding means;

and stepping means for stepping said first pointer information over a predetermined step.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2021
From: UNILOC 2017 LLC
To: ATREUS LABS LLC
Reel/Frame 057453/0790 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2018
From: UNILOC LUXEMBOURG S.A.
To: UNILOC 2017 LLC
Reel/Frame 046532/0088 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2018
From: PENDRAGON WIRELESS LLC
To: UNILOC LUXEMBOURG S.A.
Reel/Frame 045338/0601 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2012
From: IPG ELECTRONICS 503 LIMITED
To: PENDRAGON WIRELESS LLC
Reel/Frame 028594/0224 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2009
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: IPG ELECTRONICS 503 LIMITED
Reel/Frame 022203/0791 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2002
From: MEULENBROEKS, FRANCISCUS JOHANNES HENRICUS MARIA
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 013308/0369 →