High-speed and high-precision phase locked loop
View Patent ↗A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively.
1. A phase frequency detector for activating an up signal and a down signal, which are each provided to a charge pump coupled to a voltage controlled oscillator for increasing and decreasing the frequency of a vco-clock signal output from the voltage controlled oscillator, respectively, the phase frequency detector comprising:
a first dynamic, dedicated logic circuit for providing the up signal in response to a first clock signal; and
a second dynamic, dedicated logic circuit for providing the down signal in response to a second clock signal, wherein there is a linear relationship between a phase frequency difference and a duration of the up and down signals, wherein the first and second logic circuits each comprise no more than six transistors.
2. The phase frequency detector of claim 1 , further comprising a reset circuit having an output coupled to both the first and second dynamic dedicated logic circuits for providing a set signal to disable the up and down signals, in response to the later of the first and second clock signals.
3. The phase frequency detector of claim 2 , wherein the phase frequency detector has a critical path delay including switching delays from less than six gates.
4. A phase frequency detector for activating an up signal and a down signal, which are each provided to a charge pump coupled to a voltage controlled oscillator for increasing and decreasing the frequency of a vco-clock signal output from the voltage controlled oscillator, respectively, the phase frequency detector comprising:
a first dynamic, dedicated logic circuit for providing the up signal in response to a first clock signal; and
a second dynamic, dedicated logic circuit for providing the down signal in response to a second clock signal, wherein there is a linear relationship between a phase frequency difference and a duration of the up and down signals, wherein the phase frequency detector includes less than forty-four (44) transistors.
5. The phase frequency detector of claim 4 , wherein the phase frequency detector comprises no more than sixteen (16) transistors.
6. The phase frequency detector of claim 1 , wherein the phase frequency detector has a critical path delay including switching delays from no more than three gates.
7. A phase frequency detector of claim 1 , wherein there is a linear relationship between a phase frequency difference and a duration of the up and down signals for all phase frequency differences.
8. A phase lock loop to provide an oscillation signal in response to a reference clock signal comprising:
a charge pump having a first input for receiving an up signal, a second input for receiving a down signal, and an output to provide a voltage signal responsive to the up and down signals;
a voltage controlled oscillator having an input coupled to the output of the charge pump to provide the oscillation signal having a frequency responsive to the voltage signal; and
a dynamic logic phase frequency detector comprising a first input to receive a reference clock signal, a second input to receive the oscillation signal, a first output to provide the up signal, and a second output for providing the down signal, wherein a difference between the up and down signals indicates a phase difference between the reference clock signal and the oscillation signal, and wherein there is a linear relationship between a phase frequency difference and a duration of the up and down signals; wherein the phase frequency detector further comprises an up signal generator comprising a first dynamic logic circuit to provide the up signal in response to the reference clock signal; and a down signal generator comprising a second dynamic logic circuit to provide the down signal in response to the oscillation signal, wherein the first and second logic circuits each comprise no more than six transistors.
9. The phase lock loop of claim 8 wherein the phase frequency detector further comprises:
a reset circuit having an output coupled to the first and second dynamic logic circuits to provide a set signal to disable the up and down signals, respectively, in response to the reference signal or the oscillation signal.
10. A phase frequency detector to activate an up signal and a down signal, which are provided to a charge pump coupled to a voltage controlled oscillator to increase or decrease the frequency of a vco-clock signal output from the voltage controlled oscillator, respectively, the phase frequency detector comprising:
a first logic circuit to receive the vco-clock signal output from the voltage controlled oscillator and activate the up signal provided to the charge pump which increases the frequency of the vco-clock signal, if the vco-clock signal is in a first state and the down signal is inactive; and
a second logic circuit to receive a reference clock signal and activate the down signal provided to the charge pump which decreases the frequency of the vco-clock signal, if the reference clock signal is in a second state and the up signal is inactive, wherein there is a linear relationship between a phase frequency difference and a duration of the up and down signals, and wherein the first and second logic circuits each comprise no more than six transistors.
11. The phase frequency detector of claim 10 , wherein the first and second logic circuits are each reset and the up signal and the down signal are deactivated if the vco-clock signal and the reference signal are in the same state.
12. The phase lock loop of claim 10 wherein the phase frequency detector further comprises:
a reset circuit having an output coupled to the first and second dynamic logic circuits to provide a set signal to disable the up and down signals, respectively, in response to the reference signal or the oscillation signal.
13. The phase frequency detector of claim 4 , further comprising a reset circuit having an output coupled to both the first and second dynamic dedicated logic circuits for providing a set signal to disable the up and down signals, in response to the later of the first and second clock signals.
14. The phase frequency detector of claim 4 , wherein the phase frequency detector has a critical path delay including switching delays from less than six gates.
15. The phase frequency detector of claim 4 , wherein the phase frequency detector has a critical path delay including switching delays from no more than three gates.
16. A phase frequency detector of claim 4 , wherein there is a linear relationship between a phase frequency difference and a duration of the up and down signals for all phase frequencies.