Method and apparatus for improving memory operation and yield
View Patent ↗A memory circuit includes a memory interface and a first memory that receives a first write address that is associated with first data from said memory interface. A second memory stores addresses of defective memory locations found in said first memory, receives said first write address from said memory interface, compares said first write address to said addresses stored in said memory, and, if a matching address is found, writes said first data to said second memory.
1. A memory circuit comprising:
a memory interface;
a first memory that receives a first write address that is associated with first data from said memory interface;
a second memory that stores addresses of defective memory locations found in said first memory, that receives said first write address from said memory interface, that compares said first write address to said addresses stored in said second memory, and, if a matching address is found, writes said first data to said second memory.
2. The memory circuit of claim 1 wherein said second memory writes said first data to a memory location in said second memory that is associated with said matching memory address.
3. The memory circuit of claim 1 wherein said first memory writes said first write data to a memory location in said first memory corresponding to said first write address.
4. The memory circuit of claim 1 wherein said memory circuit is implemented in a hard drive controller.
5. The memory circuit of claim 1 wherein said second memory is content addressable memory (CAM).
6. The memory circuit of claim 1 wherein said first memory is error correction coding (ECC) memory that stores ECC bits.
7. A memory circuit comprising:
a memory interface;
first memory means for receiving a first write address that is associated with first data from said memory interface;
second memory means for storing addresses of defective memory locations found in said first memory means, for receiving said first write address from said memory interface, for comparing said first write address to said addresses stored in said second memory means, and, if a matching address is found, for writing said first data to said second memory means.
8. The memory circuit of claim 7 wherein said second memory means writes said first data to a memory location in said second memory means that is associated with said matching memory address.
9. The memory circuit of claim 7 wherein said first memory means writes said first write data to a memory location in said first memory means corresponding to said first write address.
10. The memory circuit of claim 7 wherein said memory circuit is implemented in a hard drive controller.
11. The memory circuit of claim 7 wherein said second memory includes content addressable memory (CAM).
12. The memory circuit of claim 7 wherein said first memory means is error correction coding (ECC) memory that stores ECC bits.