Protection of low-k dielectric in a passivation level
View Patent ↗In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.
1. A method of protecting a low-k dielectric in a passivation level, the method comprising:
exposing a portion of a passivation level to expose a metal pad in the passivation level, the passivation level being a topmost level of an integrated circuit;
covering an exposed low-k dielectric in the passivation level; and
coupling the metal pad to wiring extending out of the integrated circuit.
2. The method of claim 1 wherein covering the exposed low-k dielectric in the passivation level comprises forming a spacer.
3. The method of claim 2 wherein the spacer comprises a material selected from the group consisting of silicon nitride, UV nitride, and silicon oxynitride.
4. The method of claim 1 wherein the low-k dielectric has a dielectric constant less than about 3.9.
5. The method of claim 1 wherein covering the exposed low-k dielectric comprises forming a spacer on a sidewall that includes the exposed low-k dielectric.
6. The method of claim 1 further comprising:
cleaning a wafer containing the passivation level after covering the exposed low-k dielectric in the passivation level.
7. The method of claim 6 wherein cleaning the wafer comprises dipping the wafer in a bath of residue remover.
8. The method of claim 6 wherein cleaning the wafer comprises ashing the wafer.
9. The method of claim 1 wherein covering the exposed low-k dielectric in the passivation level comprises:
depositing a spacer material over the passivation level; and
etching the spacer material to form a spacer.
10. A method of protecting a low-k dielectric in a passivation level, the method comprising:
etching through a passivation level to expose a metal pad in a topmost metal level of an integrated circuit, the passivation level including a low-k dielectric material filling a space between the metal pad and a metal line in the topmost metal level;
depositing a spacer material over the passivation level;
etching the spacer material to form a spacer covering a sidewall including a portion of the low-k dielectric material exposed by the etching through the passivation level; and
coupling the metal pad to a lead wire extending out of the integrated circuit.
11. The method of claim 10 wherein the passivation level comprises the low-k dielectric material, a dielectric material over the low-k dielectric material, and a topside material over the dielectric material.
12. The method of claim 11 wherein the dielectric material comprises silicon dioxide.
13. The method of claim 11 wherein the topside material comprises silicon nitride.