IP Library Granted Patent US 6,957,325
Granted Patent B1
US 6,957,325 · App. 10/188,247 · Granted Oct 18, 2005

System and method for detecting program hazards in processors with unprotected pipelines

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Quick Facts
Patent No.
US 6,957,325
App. No.
10/188,247
Granted
Oct 18, 2005
Kind
B1
Abstract

A process and system for analyzing executable portion of computer code for processors with unprotected pipelines is provided. The process assumes a worst set of current processor states; analyzes plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and adjusts the worst set of current processor states based on program annotations to the computer instruction.

Claims (33)

1. A method for analyzing executable portion of computer code for processors with unprotected pipelines, comprising:

assuming a worst set of current processor states for a processor with unprotected pipelines;

analyzing plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and

adjusting the worst set of current processor states based on program annotations to the computer instruction.

2. The method of claim 1 , further comprising:

determining if the adjusted set of current machine states is different from a previously determined set of processor states; and

updating the computed induced set of processor states associated with the instruction, if the adjusted set of current processor states is different from the previously determined set of processor states.

3. The method of claim 2 , further comprising:

using the computed set of processor states for determining hazards in another computer instruction.

4. A computer-readable medium storing computer-executable process steps of a process for use in a computer system for analyzing executable portion of computer code for processors with unprotected pipelines, comprising:

assuming a worst set of current processor states;

analyzing plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and

adjusting the worst set of current processor states based on program annotations to the computer instruction.

5. The computer readable medium of claim 4 , further comprising:

determining if the adjusted set of current machine states is different from a previously determined set of processor states; and

updating the computed induced set of processor states associated with the instruction, if the adjusted set of current processor states is different from the previously determined set of processor states.

6. The computer readable medium of claim 4 , further comprising:

using the computed set of processor states for determining hazards in the next computer instruction.

7. Computer-executable code for analyzing executable portion of computer code for processors with unprotected pipelines, comprising:

assuming a worst set of current processor states;

analyzing plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and adjusting the worst set of current processor states based on program annotations to the computer instruction.

8. Computer-executable code of claim 7 , further comprising:

determining if the adjusted set of current machine states is different from a previously determined set of processor states; and

updating the computed induced set of processor states associated with the instruction, if the adjusted set of current processor states is different from the previously determined set of processor states.

9. Computer-executable code of claim 7 , further comprising:

using the computed set of processor states for determining hazards in another computer instruction.

10. A system for analyzing executable portion of computer code, comprising:

a processor that analyzes plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and

adjusting a set of current processor states based on program annotations to the computer instruction.

11. The system of claim 10 , wherein the processor

determines if the adjusted set of current processor states is different from a previously determined set of processor states; and

updates the computed induced set of processor states associated with the instruction, if the adjusted set of current processor states is different from the previously determined set of processor states.

12. The system of claim 10 , wherein the processor uses the computed set of processor states for determining hazards in another computer instruction.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2017
From: MINDSPEED TECHNOLOGIES, LLC
To: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
Reel/Frame 044791/0600 →
CHANGE OF NAME Recorded Aug 10, 2016
From: MINDSPEED TECHNOLOGIES, INC.
To: MINDSPEED TECHNOLOGIES, LLC
Reel/Frame 039645/0264 →
SECURITY INTEREST Recorded May 9, 2014
From: M/A-COM TECHNOLOGY SOLUTIONS HOLDINGS, INC.; MINDSPEED TECHNOLOGIES, INC.; BROOKTREE CORPORATION
To: GOLDMAN SACHS BANK USA
Reel/Frame 032859/0374 →
RELEASE OF SECURITY INTEREST Recorded May 9, 2014
From: JPMORGAN CHASE BANK, N.A.
To: MINDSPEED TECHNOLOGIES, INC.
Reel/Frame 032861/0617 →
SECURITY INTEREST Recorded Mar 21, 2014
From: MINDSPEED TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 032495/0177 →
RELEASE OF SECURITY INTEREST Recorded Oct 24, 2013
From: CONEXANT SYSTEMS, INC
To: MINDSPEED TECHNOLOGIES, INC
Reel/Frame 031494/0937 →
SECURITY AGREEMENT Recorded Oct 8, 2003
From: MINDSPEED TECHNOLOGIES, INC.
To: CONEXANT SYSTEMS, INC.
Reel/Frame 014546/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2003
From: CONEXANT SYSTEMS, INC.
To: MINDSPEED TECHNOLOGIES, INC.
Reel/Frame 014568/0275 →