Image sensing system and method
View Patent ↗A cost-effective image capture apparatus is presented which achieves high shutter speed without blurring the captured image or introducing noise. The apparatus uses standard 4T pixels to store exposure information on the pixel itself and employs a near simultaneous reset mechanism to reset the pixels, thereby achieving high-speed image capture without increasing the per pixel die area for extra storage or incurring unwanted current spikes and noise due to simultaneous resets.
1. A system for high-speed image capture, comprising:
a first clock;
a plurality of pixels being arranged in a plurality of pixel groups, the plurality of pixel groups having a first pixel group, each pixel in the plurality of pixels having a photo sensitive element and a storage element, the photo sensitive element producing an output indicative of incoming light; and
a control element coupled to the plurality of pixels, the control element resetting the plurality of pixel groups iteratively and at the rate of one pixel group in the plurality of pixel groups per one c clock cycle of the first clock, and the control element transferring the outputs of a plurality of photo sensitive elements in the first pixel group to a plurality of storage elements in the first pixel group, the transferring proceeding at the rate of one pixel group in the plurality of pixel groups per one c′ clock cycle of the first clock and occurring simultaneously for all pixels in the first pixel group, wherein the first clock generates a first clock signal at a first rate, the first clock signal generating a second clock signal at a second rate, the second clock signal triggering an analog-to-digital converter (ADC).
2. A system for high-speed image capture, comprising:
a first clock;
a plurality of pixels being arranged in a plurality of pixel groups, the plurality of pixel groups having a first pixel group, each pixel in the plurality of pixels having a photo sensitive element and a storage element, the photo sensitive element producing an output indicative of incoming light; and
a control element coupled to the plurality of pixels, the control element resetting the plurality of pixel groups iteratively and at the rate of one pixel group in the plurality of pixel groups per one c clock cycle of the first clock, and the control element transferring the outputs of a plurality of photo sensitive elements in the first pixel group to a plurality of storage elements in the first pixel group, the transferring proceeding at the rate of one pixel group in the plurality of pixel groups per one c′ clock cycle of the first clock and occurring simultaneously for all pixels in the first pixel group, wherein the first clock rate operates at a first frequency which is less than a multiple of the second clock rate operating at a second frequency.
3. A system for high-speed image capture, comprising:
a first clock;
a plurality of pixels being arranged in a plurality of pixel groups, the plurality of pixel groups having a first pixel group, each pixel in the plurality of pixels having a photo sensitive element and a storage element, the photo sensitive element producing an output indicative of incoming light; and
a control element coupled to the plurality of pixels, the control element resetting the plurality of pixel groups iteratively and at the rate of one pixel group in the plurality of pixel groups per one c clock cycle of the first clock, and the control element transferring the outputs of a plurality of photo sensitive elements in the first pixel group to a plurality of storage elements in the first pixel group, the transferring proceeding at the rate of one pixel group in the plurality of pixel groups per one c′ clock cycle of the first clock and occurring simultaneously for all pixels in the first pixel group, wherein the first clock rate operates at a first frequency which is a multiple of the second clock rate operating at a second frequency.
4. The system of claim 1 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises one row of the array, c=1, and c′=1.
5. The system of claim 1 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises m rows of the array, and m>1.
6. The system of claim 1 , wherein each pixel in the plurality of pixels comprises a four-transistor (4T) configuration.
7. The system of claim 1 , wherein the photo sensitive element of a pixel in the plurality of pixels comprises a photodiode or a photogate or a PIN diode.
8. The system of claim 1 , wherein the storage element of a pixel in the plurality of pixels comprises a capacitor.
9. A method for operating an image sensor, the image sensor having a plurality of pixels, the plurality of pixels having a plurality of pixel groups, the plurality of pixel groups having a first pixel group, each pixel in the plurality of pixels having a photo sensitive element and a storage element, the photo sensitive element producing an output indicative of incoming light, comprising:
(a) resetting the first pixel group in the plurality of pixel groups according to a timing of a first clock, the resetting occurring simultaneously for all pixels in the first pixel group;
(b) iteratively repeating the resetting step (a) and at a rate of one pixel group in the plurality of pixel groups per one c clock cycle of the first clock;
(c) transferring the outputs of a plurality of photo sensitive elements in the first pixel group to a plurality of storage elements in the first pixel group, the transferring occurring simultaneously for all the pixels in the first pixel group; and
(d) iteratively repeating the transferring step (c) and at a rate of one pixel group in the plurality of pixel groups per one c′ clock cycle of the first clock, wherein the first clock generates a first clock signal at a first rate, the first clock signal generating a second clock signal at a second rate, the second clock signal triggering an analog-to-digital converter (ADC).
10. The method of claim 9 , wherein c>0 and c′>0.
11. The method of claim 9 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises one row of the array, c=1, and c′=1.
12. The method of claim 9 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises m rows of the array, and m>1.
13. The method of claim 9 , wherein each pixel in the plurality of pixels comprises a four-transistor (4T) configuration.
14. The method of claim 9 , wherein the photo sensitive element of a pixel in the plurality of pixels comprises a photodiode or a photogate or a PIN diode.
15. The method of claim 9 , wherein the storage element of a pixel in the plurality of pixels comprises a capacitor.
16. A system for high-speed image capture, comprising:
an array of pixels having rows of pixels, a first row in the rows of pixels having a first pixel and a second pixel, the first pixel having a first photo sensitive element and a first storage element, the first photo sensitive element producing a first output indicative of a first incoming light, the second pixel having a second photo sensitive element and a second storage element, the second photo sensitive element producing a second output indicative of a second incoming light; and
a control element, coupled to the array of pixels, the control element resetting rows of pixels iteratively at a rate of one row per one c clock cycle of a first clock, the control element transferring the first output of the first photo sensitive element to the first storage element, the control element transferring the second output of the second photo sensitive element to the second storage element, the control element transferring at the rate of one row per one c′ clock cycle of the first clock, the transferring occurring simultaneously for the first and second pixels in the first row, wherein the first clock generates a first clock signal at a first rate, the first clock signal generating a second clock signal at a second rate, the second clock signal triggering an analog-to-digital converter (ADC).
17. The system of claim 1 , wherein c>0 and c′>0.
18. The system of claim 2 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises one row of the array, c=1, and c′=1.
19. The system of claim 2 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises m rows of the array, and m>1.
20. The system of claim 2 , wherein each pixel in the plurality of pixels comprises a four-transistor (4T) configuration.
21. The system of claim 2 , wherein the photo sensitive element of a pixel in the plurality of pixels comprises a photodiode or a photogate or a PIN diode.
22. The system of claim 2 , wherein the storage element of a pixel in the plurality of pixels comprises a capacitor.
23. The system of claim 2 , wherein c>0 and c′>0.
24. The system of claim 3 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises one row of the array, c=1, and c′=1.
25. The system of claim 3 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises m rows of the array, and m>1.
26. The system of claim 3 , wherein each pixel in the plurality of pixels comprises a four-transistor (4T) configuration.
27. The system of claim 3 , wherein the photo sensitive element of a pixel in the plurality of pixels comprises a photodiode or a photogate or a PIN diode.
28. The system of claim 3 , wherein the storage element of a pixel in the plurality of pixels comprises a capacitor.
29. The system of claim 3 , wherein c>0 and c′>0.
30. A method for operating an image sensor, the image sensor having a plurality of pixels, the plurality of pixels having a plurality of pixel groups, the plurality of pixel groups having a first pixel group, each pixel in the plurality of pixels having a photo sensitive element and a storage element, the photo sensitive element producing an output indicative of incoming light, comprising:
(a) resetting the first pixel group in the plurality of pixel groups according to a timing of a first clock, the resetting occurring simultaneously for all pixels in the first pixel group;
(b) iteratively repeating the resetting step (a) and at a rate of one pixel group in the plurality of pixel groups per one c clock cycle of the first clock;
(c) transferring the outputs of a plurality of photo sensitive elements in the first pixel group to a plurality of storage elements in the first pixel group, the transferring occurring simultaneously for all the pixels in the first pixel group; and
(d) iteratively repeating the transferring step (c) and at a rate of one pixel group in the plurality of pixel groups per one c′ clock cycle of the first clock,
wherein the first clock rate operates at a first frequency which is less than a multiple of the second clock rate operating at a second frequency.
31. The method of claim 30 , wherein c>0 and c′>0.
32. The method of claim 30 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises one row of the array, c=1, and c′=1.
33. The method of claim 30 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises m rows of the array, and m>1.
34. The method of claim 30 , wherein each pixel in the plurality of pixels comprises a four-transistor (4T) configuration.
35. The method of claim 30 , wherein the photo sensitive element of a pixel in the plurality of pixels comprises a photodiode or a photogate or a PIN diode.
36. The method of claim 30 , wherein the storage element of a pixel in the plurality of pixels comprises a capacitor.
37. A method for operating an image sensor, the image sensor having a plurality of pixels, the plurality of pixels having a plurality of pixel groups, the plurality of pixel groups having a first pixel group, each pixel in the plurality of pixels having a photo sensitive element and a storage element, the photo sensitive element producing an output indicative of incoming light, comprising:
(a) resetting the first pixel group in the plurality of pixel groups according to a timing of a first clock, the resetting occurring simultaneously for all pixels in the first pixel group;
(b) iteratively repeating the resetting step (a) and at a rate of one pixel group in the plurality of pixel groups per one c clock cycle of the first clock;
(c) transferring the outputs of a plurality of photo sensitive elements in the first pixel group to a plurality of storage elements in the first pixel group, the transferring occurring simultaneously for all the pixels in the first pixel group; and
(d) iteratively repeating the transferring step (c) and at a rate of one pixel group in the plurality of pixel groups per one c′ clock cycle of the first clock,
wherein the first clock rate operates at a first frequency which is a multiple of the second clock rate operating at a second frequency.
38. The method of claim 37 , wherein c>0 and c′>0.
39. The method of claim 9 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises one row of the array, c=1, and c′=1.
40. The method of claim 37 , wherein the plurality of pixels comprises an array, each pixel group in the plurality of pixel groups comprises m rows of the array, and m>1.
41. The method of claim 37 , wherein each pixel in the plurality of pixels comprises a four-transistor (4T) configuration.
42. The method of claim 37 , wherein the photo sensitive element of a pixel in the plurality of pixels comprises a photodiode or a photogate or a PIN diode.
43. The method of claim 37 , wherein the storage element of a pixel in the plurality of pixels comprises a capacitor.
44. A system for high-speed image capture, comprising:
an array of pixels having rows of pixels, a first row in the rows of pixels having a first pixel and a second pixel, the first pixel having a first photo sensitive element and a first storage element, the first photo sensitive element producing a first output indicative of a first incoming light, the second pixel having a second photo sensitive element and a second storage element, the second photo sensitive element producing a second output indicative of a second incoming light; and
a control element, coupled to the array of pixels, the control element resetting rows of pixels iteratively at a rate of one row per one c clock cycle of a first clock, the control element transferring the first output of the first photo sensitive element to the first storage element, the control element transferring the second output of the second photo sensitive element to the second storage element, the control element transferring at the rate of one row per one c′ clock cycle of the first clock, the transferring occurring simultaneously for the first and second pixels in the first row, wherein the first clock rate operates at a first frequency which is less than a multiple of the second clock rate operating at a second frequency.
45. A system for high-speed image capture, comprising:
an array of pixels having rows of pixels, a first row in the rows of pixels having a first pixel and a second pixel, the first pixel having a first photo sensitive element and a first storage element, the first photo sensitive element producing a first output indicative of a first incoming light, the second pixel having a second photo sensitive element and a second storage element, the second photo sensitive element producing a second output indicative of a second incoming light; and
a control element, coupled to the array of pixels, the control element resetting rows of pixels iteratively at a rate of one row per one c clock cycle of a first clock, the control element transferring the first output of the first photo sensitive element to the first storage element, the control element transferring the second output of the second photo sensitive element to the second storage element, the control element transferring at the rate of one row per one c′ clock cycle of the first clock, the transferring occurring simultaneously for the first and second pixels in the first row, wherein the first clock rate operates at a first frequency which is a multiple of the second clock rate operating at a second frequency.