Method and system for optimizing pre-fetch memory transactions
View Patent ↗A method of determining whether to issue a pre-fetch transaction in a memory control system comprising generating a pre-fetch threshold dependent on a demand load of a memory controller, calculating a probability measure of pre-fetch accuracy, comparing the threshold with the calculated probability measure, and determining whether to issue a pre-fetch transaction based upon the comparison of the threshold with the calculated probability measure is provided. A pre-fetch apparatus implemented in a memory control system comprising a pre-fetch threshold generator operable to output a pre-fetch threshold in response to a signal indicative of a memory controller demand load, and a comparator circuit operable to compare the pre-fetch threshold and a probability measure of pre-fetch accuracy, wherein the pre-fetch apparatus issues a pre-fetch transaction on the basis of the comparison by the comparator is provided.
1. A method of determining whether to issue a pre-fetch transaction in a memory control system, comprising:
generating a pre-fetch threshold dependent on a demand load of a memory controller;
calculating a probability measure of pre-fetch accuracy;
comparing the threshold with the calculated probability measure; and
determining whether to issue a pre-fetch transaction based upon the comparison of the threshold with the calculated probability measure.
2. The method according to claim 1 , wherein generating a pre-fetch threshold further comprises obtaining a count of memory transactions maintained in a heap of a memory controller.
3. The method according to claim 1 , wherein generating a pre-fetch threshold further comprises obtaining a count of memory transactions maintained in a heap of a first memory controller and a count of memory transactions maintained in a heap of a second memory controller.
4. The method according to claim 3 , wherein generating a pre-fetch threshold further comprises generating the pre-fetch threshold as a function of the greater of the counts.
5. The method according to claim 1 , wherein generating a pre-fetch threshold further comprises generating the pre-fetch threshold as a function of a count of memory transactions maintained in the memory controller.
6. The method according to claim 1 , wherein calculating a probability measure further comprises:
maintaining a pre-defined number of calculated pre-fetch addresses;
monitoring memory access requests of a processor; and
accumulating a count of the calculated pre-fetch addresses that address information targeted by the monitored memory access requests.
7. The method according to claim 6 , wherein maintaining a predefined number of calculated pre-fetch addresses further comprising maintaining the calculated pre-fetch addresses in an array.
8. The method according to claim 1 , wherein generating a pre-fetch threshold further comprises adjusting the threshold in correspondence with changes in the demand load.
9. The method according to claim 8 , wherein adjusting the threshold further comprises increasing the threshold in correspondence with an increase in the demand load.
10. The method according to claim 8 , wherein adjusting the threshold further comprises decreasing the threshold in correspondence with a decrease in the demand load.
11. A pre-fetch apparatus implemented in a memory control system, comprising:
a pre-fetch threshold generator operable to output a pre-fetch threshold in response to a signal indicative of a memory controller demand load; and
a comparator circuit operable to compare the pre-fetch threshold and a probability measure of pre-fetch accuracy, wherein the pre-fetch apparatus issues a pre-fetch transaction on the basis of the comparison by the comparator.
12. The pre-fetch apparatus according to claim 11 , wherein the pre-fetch threshold generator is operable to select a threshold from a plurality of thresholds maintained in respective programmable registers.
13. The pre-fetch apparatus according to claim 11 , further comprising a pre-fetch address generator operable to calculate a pre-fetch address from a memory transaction.
14. The pre-fetch apparatus according to claim 13 , further comprising a data structure operable to store a pre-defined number of calculated pre-fetch addresses.
15. Th pre-fetch apparatus according to claim 14 , wherein each of the calculated pre-fetch addresses has a pre-fetch flag associated therewith, a pre-fetch flag asserted when the associated pre-fetch address is subject to the memory transaction.
16. The pre-fetch apparatus according to claim 14 , further comprising a pre-fetch hit rate calculator operable to monitor memory access requests and accumulate a count of previously calculated pre-fetch addresses maintained in the data structure that respectively address information of the monitored memory access requests.
17. The pre-fetch apparatus according to claim 16 , wherein the probability measure is the accumulated count.
18. The pre-fetch apparatus according to claim 11 , wherein the pre-fetch threshold generator is a multiplexer having the signal indicative of the memory controller demand load applied to a select input thereof.
19. The pre-fetch apparatus according to claim 11 , wherein the pre-fetch threshold is selected from a plurality of pre-fetch thresholds based on a heap load of a memory controller, the probability measure is a pre-fetch hit rate equivalent to a number of memory access hits of a pre-determined number of recently calculated pre-fetch addresses, the pre-fetch transaction issued if the pre-fetch hit rate is equal or greater than the threshold.
20. The pre-fetch apparatus according to claim 19 , wherein the pre-fetch threshold increases as the heap load increases, the pre-fetch threshold decreasing as the heap load decreases.
21. The pre-fetch apparatus according to claim 19 , wherein the heap load is derived from a plurality of heap loads of a respective plurality of memory controller heaps.