High-definition de-interlacing and frame doubling circuit and method
View Patent ↗A combined de-interlacing and frame doubling system ( 114, 114′ and 114″ ) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism ( 116, 116′ and 116″ ) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit ( 1140 1 , 1140′ 1 , 1140″ ) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.
1. A combined de-interlacing and frame doubling system, comprising:
a frame memory mechanism for storing frames of interlaced video data, the frames having a prescribed frame rate;
first and second combined de-interlacing and frame-doubling circuit for each pulling each of two frames of video data from the frame memory mechanism at twice the frame rate and for performing a full de-interlacing function at half the frame rate time so as to perform two de-interlacing operations, once during each double rate frame, to generate a progressive, frame doubled signal for receipt at a display device, wherein the first and second combined de-interlacing and frame doubling circuits, each reads video data from the frame memory mechanism from two sequential lines at the same time, such that each circuit reads separate lines.
2. The apparatus according to claim 1 further including first and second line memories for receiving updated video data from the first and second combined de-interlacing and frame doubling circuits, respectively, and for writing such updated video to the second and first de-interlacing circuits, respectively.
3. The apparatus according to claim 1 wherein the combined de-interlacing and frame doubling circuit includes:
a Motion Calculator for generating an updated motion for each successive Video line N (where N is an non-zero integer index value that successively increases by unity for each successive de-interlacing operation.) in accordance with video information stored in the frame memory mechanism; and
a calculation block for calculating at least one de-interlaced Present Field Video Line in accordance with the updated motion from the Motion Calculator and stored video information in the frame memory mechanism.
4. The apparatus according to claim 3 wherein the calculation block calculates two successive de-interlaced Present Field Video Lines.
5. The apparatus according to claim 3 wherein the frame memory mechanism system comprises:
a memory controller:
a physical interface coupling the at least one DRAM to the memory controller; and
a First-In First Out (FIFO) block containing a plurality of FIFO elements, each serving to hold data transferred between the at least one DRAM and the de-interlacing circuit.
6. A combined de-interlacing and frame doubling system, comprising:
a frame memory mechanism for storing frames of interlaced video data, the frames having a prescribed frame rate;
a first combined de-interlacing and frame doubling circuit for pulling video data from the frame memory mechanism associated with a first pair of successive video lines and for performing a full de-interlacing function at half the frame rate time so as to perform two de-interlacing operations, once during each double rate frame, to generate a first pair of successive de-interlaced Present Field Video Lines; and;
a second combined de-interlacing and frame doubling circuit for pulling video data from the frame memory mechanism associated with a second pair of successive video lines and for performing a full de-interlacing function in parallel with the de-interlacing operation performed by the first de-interlacing circuit at half the frame rate time so as to perform two de-interlacing operations, once during each double rate frame, to generate a second pair of successive de-interlaced Present Field Video Lines.
7. The apparatus according to claim 6 further including first and second line memories for receiving updated video data from the first and second de-interlacing circuits, respectively, and for writing such updated video to the second and first de-interlacing circuits, respectively.
8. The apparatus according to claim 6 wherein each combined de-interlacing and frame doubling circuit includes:
a Motion Calculator for generating an updated motion for each successive Video line N (where N is an non-zero integer index value that successively increases by unity for each successive de-interlacing operation) in accordance with video information stored in the frame memory mechanism; and
a calculation block for calculating the de-interlaced pair of Present Field Video Lines in accordance with the updated motion from the Motion Calculator and stored video information in the frame memory mechanism.
9. The apparatus according to claim 6 wherein the frame memory mechanism includes at least one dynamic random access memory.
10. The apparatus according to claim 9 wherein the frame memory mechanism system further includes:
a memory controller;
a physical interface coupling the at least one DRAM to the memory controller; and
a First-in First Out (FIFO) block containing a plurality of FIFO elements, each serving to hold data transferred between the at least one DRAM and the de-interlacing circuit.