Driver circuits and methods
View Patent ↗In one system embodiment, the system is characterized by: a differential amplifier including but not limited to at least one amplifying transistor having an emitter coupled directly to a ground. In one embodiment of a method of making a system, the method is characterized by: operably coupling at least one amplifying transistor of a differential amplifier directly to a ground. In one embodiment of a method of driving a system, the method is characterized by: driving at least one amplifying transistor of a differential amplifier with an emitter-follower feedback loop. In one system embodiment, the system is characterized by: a differential amplifier including but not limited to a first amplifying transistor having a base operably coupled with a first emitter-follower feedback loop.
1. A driver circuit, comprising:
a first input stage comprising:
a first transistor coupled between a first node and a second node and having a control terminal coupled to a third node;
a second transistor coupled between a fourth node and the second node and having a control terminal coupled to the third node;
a third transistor coupled between a fifth node and the third node and having a control terminal coupled to the fourth node; and
a first resistor coupled between the third node and the second node;
a second input stage comprising:
a fourth transistor coupled between a sixth node and the second node and having a control terminal coupled to a seventh node;
a fifth transistor coupled between an eighth node and the second node and having a control terminal coupled to the seventh node;
a sixth transistor coupled between a ninth node and the seventh node and having a control terminal coupled to the eighth node; and
a second resistor coupled between the seventh node and the second node; and
an output stage comprising:
a seventh transistor coupled between the first node and a tenth node and having a control terminal coupled to an eleventh node; and
an eighth transistor coupled between the sixth node and a twelfth node and having a control terminal coupled to the eleventh node.
2. The driver circuit of claim 1 , further comprising:
a third resistor coupled between the tenth node and a thirteenth node; and
a fourth resistor coupled between the twelfth node and a fourteenth node.
3. The driver circuit of claim 2 wherein the second node is a ground node.
4. The driver circuit of claim 1 wherein the first transistor is an NPN transistor.
5. The driver circuit of claim 3 wherein the fifth node, the ninth node, the eleventh node, the thirteenth node and the fourteenth node are coupled to a reference voltage.
6. The driver circuit of claim 2 , further comprising:
a ninth transistor coupled between the fourth node and a fifteenth node and having a control terminal;
a tenth transistor coupled between the eighth node and the fifteenth node and having a control terminal;
a fifth resistor coupled between the fourth node and a sixteenth node; and
a sixth resistor coupled between the eighth node and the sixteenth node.
7. The driver circuit of claim 6 , further comprising:
a first current source coupled to the fifteenth node; and
a second current source coupled to the sixteenth node.
8. The driver circuit of claim 7 wherein the second current source is configured to produce a modulating current.
9. The driver circuit of claim 6 wherein the second node is coupled to a ground.
10. The driver circuit of claim 9 wherein the fifth node, the ninth node, the eleventh node, the thirteenth node and the fourteenth node are coupled to a reference voltage.
11. A driver circuit, comprising:
a first input stage comprising:
a first transistor coupled between a first node and a second node and having a control terminal coupled to a third node;
a second transistor coupled between a fourth node and the second node and having a control terminal coupled to the third node;
a third transistor coupled between a fifth node and the third node and having a control terminal coupled to the fourth node; and
a first resistor coupled between the third node and the second node;
a second input stage comprising:
a fourth transistor coupled between a sixth node and the second node and having a control terminal coupled to a seventh node;
a fifth transistor coupled between an eighth node and the second node and having a control terminal coupled to the seventh node;
a sixth transistor coupled between a ninth node and the seventh node and having a control terminal coupled to the eighth node; and
a second resistor coupled between the seventh node and the second node;
an output stage comprising:
a seventh transistor coupled between the first node and a tenth node and having a control terminal coupled to an eleventh node; and
an eighth transistor coupled between the sixth node and a twelfth node and having a control terminal coupled to the eleventh node;
a ninth transistor coupled between the fourth node and a thirteenth node and having a control terminal;
a tenth transistor coupled between the eighth node and the thirteenth node and having a control terminal;
a third resistor coupled between the fourth node and a fourteenth node; and a fourth resistor coupled between the eighth node and the fourteenth node.
12. The driver circuit of claim 11 further comprising:
a first current source coupled to the thirteenth node; and
a second current source coupled to the fourteenth node.
13. The driver circuit of claim 11 wherein the second node is coupled to a ground.
14. The driver circuit of claim 13 wherein the fifth node, the ninth node, the tenth node, the eleventh node, and the twelfth node are coupled to a reference voltage.
15. A driver circuit, comprising:
a first input stage comprising:
a first transistor coupled between a first node and a second node and having a control terminal coupled to a third node;
a second transistor coupled between a fourth node and the second node and having a control terminal coupled to the third node;
a third transistor coupled between a fifth node and the third node and having a control terminal coupled to the fourth node; and
a first resistor coupled between the third node and the second node;
a second input stage comprising:
a fourth transistor coupled between a sixth node and the second node and having a control terminal coupled to a seventh node;
a fifth transistor coupled between an eighth node and the second node and having a control terminal coupled to the seventh node;
a sixth transistor coupled between a ninth node and the seventh node and having a control terminal coupled to the eighth node; and
a second resistor coupled between the seventh node and the second node;
an output stage comprising:
a seventh transistor coupled between the first node and a tenth node and having a control terminal coupled to an eleventh node; and
an eighth transistor coupled between the sixth node and a twelfth node and having a control terminal coupled to the eleventh node;
a thirteenth node coupled to the fourth node and the eighth node; and
a modulating current source coupled to the thirteenth node.
16. A modulator having a driver, the driver comprising:
a first input stage comprising:
a first transistor coupled between a first node and a second node and having a control terminal coupled to a third node;
a second transistor coupled between a fourth node and the second node and having a control terminal coupled to the third node;
a third transistor coupled between a fifth node and the third node and having a control terminal coupled to the fourth node; and
a first resistor coupled between the third node and the second node;
a second input stage comprising:
a fourth transistor coupled between a sixth node and the second node and having a control terminal coupled to a seventh node;
a fifth transistor coupled between an eighth node and the second node and having a control terminal coupled to the seventh node;
a sixth transistor coupled between a ninth node and the seventh node and having a control terminal coupled to the eighth node; and
a second resistor coupled between the seventh node and the second node; and
an output stage comprising:
a seventh transistor coupled between the first node and a tenth node and having a control terminal coupled to an eleventh node; and
an eighth transistor coupled between the sixth node and a twelfth node and having a control terminal coupled to the eleventh node.