Memory cell having a second transistor for holding a charge value

1. A memory cell, comprising:

semiconductor material;

a capacitor formed in said semiconductor material and having an inner electrode and an outer electrode;

a first transistor for performing an operation selected from the group consisting of reading an information item from said capacitor and writing an information item to said capacitor;

an insulating layer electrically insulating said inner electrode from said outer electrode; and

a second transistor formed in said semiconductor material;

said second transistor having a first contact region disposed adjoining said inner electrode thereby being directly connected to said inner electrode;

said second transistor having a control contact region formed by said inner electrode of said capacitor;

said second transistor having a second contact region for connecting to a voltage source;

said second transistor enabling charging of said capacitor from a charge provided by the voltage source;

said insulating layer having a region running along said outer electrode, said second contact region, and up towards said first contact region, said region of said insulating layer having a constant thickness allowing said second transistor to go into a conductive state when said inner electrode carries a high logic level.

2. The memory cell according to claim 1 , comprising:

a first electrically conductive region formed in said semiconductor material, said first conductive region constituting said outer electrode of said capacitor; and

a second conductive region formed in said semiconductor material;

said insulating layer electrically insulating said inner electrode of said capacitor from said semiconductor material;

said first conductive region adjoining said insulating layer;

said first contact region of said second transistor being formed in said semiconductor material;

said first contact region of said second transistor being conductively connected to said inner electrode;

said first contact region being formed at a distance from said first conductive region formed in said semiconductor material;

said semiconductor material having a doping of a first conductivity type;

said first contact region, said inner electrode and said second region having a doping of a second conductivity type being oppositely doped with respect to said doping of said semiconductor material of said first conductivity type;

said first contact region and said first conductive region adjoining said insulating layer;

said second conductive region adjoining said insulating layer;

said first conductive region having the doping of said first conductivity type;

said second conductive region being formed between said first contact region and said first conductive region; and

said second contact region of said second transistor being formed by said second conductive region.

3. The memory cell according to claim 1 , wherein the voltage source charges said capacitor during the conductive state of said second transistor.

4. The memory cell according to claim 1 , wherein the voltage source charges said capacitor during the conductive state of said second transistor for stabilizing a charge on said inner electrode offsetting undesirable leakage currents.

5. The memory cell according to claim 1 , wherein said constant thickness of said region of said insulating layer is selected for allowing said second transistor to conduct if a high logic level is impressed on said capacitor.

6. The memory cell according to claim 5 , wherein said constant thickness of said region of said insulating layer is selected for allowing said second transistor to be nonconducting if a low logic level is impressed on said capacitor.

7. A memory cell, comprising:

semiconductor material;

a capacitor formed in said semiconductor material and having an inner electrode and an outer electrode;

a first transistor for performing an operation selected from the group consisting of reading an information item from said capacitor and writing an information item to said capacitor;

an insulating layer electrically insulating said inner electrode from said outer electrode;

a first conductive region formed from a positively doped semiconductor material;

a second transistor formed in said semiconductor material;

said second transistor having a first contact region disposed adjoining said inner electrode thereby being directly connected to said inner electrode;

said second transistor having a control contact region formed by said inner electrode of said capacitor;

said second transistor having a second contact region for connecting to a voltage source;

said second transistor enabling charging of said capacitor;

said insulating layer having a region running along said outer electrode, said second contact region, and up towards said first contact region, said region of said insulating layer having a constant thickness;

said inner electrode, said first contact region and said second contact region being formed from a negatively doped semiconductor material; and

said semiconductor material being positively doped.