Processing of quinary data
View Patent ↗A FIR filter in a Gigabit transceiver in which data words are represented in three bits: SIGN representing word sign, SHIFT representing requirement for a shift operation, and ZERO indicating whether the word is zero. An AND gate ANDs an input coefficient and the ZERO bit, an XOR gate XORs the SIGN bit and the output of the AND gate, and a multiplier left-shifts the coefficient using the SHIFT bit and the output of the XOR gate. The circuit has a very low gate count.
1. A communication circuit comprising a multiplier for receiving a PAM-5 quinary data word in which a binary bit represents each of a word sign, requirement for a shift operation, and whether the word is zero, said multiplier including an AND gate for ANDing an input coefficient and the zero-representing bit, and an XOR gate for performing an XOR operation with the sign-representing bit and an output of said AND gate to negate the coefficient if the coefficient is non-zero and the zero-representing bit and the sign-representing bit are both zero, or if the coefficient, the zero-representing bit and the sign-representing bit are all non-zero.
2. The communication circuit as claimed in claim 1 , wherein the multiplier further comprises a multiplexer for left-shifting the coefficient using the shift-representing bit and the output of the XOR gate.
3. The communication circuit as claimed in claim 1 , wherein the multiplier further comprises means for correcting a least significant bit (LSB) of the product where the data is negative.
4. The communication circuit as claimed in claim 3 , wherein said correction means is in a sum-of-products block for a set of multipliers.
5. A finite impulse response (FIR) filter comprising a tap delay line; a plurality of multipliers, each multiplier configured to receive a PAM-5 quinary data word in which a binary bit represents each of a word sign, requirement for a shift operation, and whether the word is zero; and a sum-of-products (SOP) block, each multiplier including:
AND gates, each for ANDing an input coefficient and a zero-representing bit;
XOR gates, each for performing an XOR operation with the sign-representing bit and an output of said AND gates to negate the coefficient if the coefficient is zero and the zero-representing bit and the sign-representing bit are both non-zero; and
a multiplexer for left-shifting the coefficient using the shift-representing bit and the output of the XOR gates.
6. The finite impulse response (FIR) filter as claimed in claim 5 , wherein the filter further comprises a correction circuit comprising means for maintaining a count of the sum of all sign values in the tap delay line, and means in the SOP block for adding said count to the sum.
7. The finite impulse response (FIR) filter as claimed in claim 6 , wherein the correction circuit comprises means for maintaining said count by monitoring only the sign values of the first and the last tap delay line registers.
8. A finite impulse response (FIR) filter comprising:
a tap delay line;
a plurality of multipliers, each multiplier configured to receive a PAM-5 quinary data word in which a binary bit represents each of a word sign, requirement for a shift operation, and whether the word is zero, each multiplier including,
an AND gate for ANDing an input coefficient and a zero-representing bit;
an XOR gate for performing an XOR operation with the sign-representing bit and an output of said AND gate to negate the coefficient if the coefficient, the zero-representing bit and the sign-representing bit are all zero, or if the coefficient is zero and the zero-representing bit and the sign-representing bit are both non-zero;
a multiplexer for left-shifting the coefficient using the shift-representing bit and the output of the XOR gate; and
a correction circuit configured to maintain a count of the sum of all sign values in the tap delay line by monitoring only the sign values of the first and the last tap delay line registers.