Duty cycle corrector

1. A duty cycle correction device for generating an output clock signal with a desired duty cycle based on an input clock signal, comprising:

a pulse generator that inputs the input clock signal and generates a reset signal;

a voltage controlled delay element that inputs the reset signal and a bias signal and generates a modified reset signal;

a flip-flop configured to generate the output clock signal, wherein the input clock signal and the modified reset signal serve as an inputs to the flip-flop; and

a duty cycle controller that inputs the output clock signal and generates the bias signal therefrom.

2. The duty cycle correction device of claim 1 , wherein the duty cycle controller monitors a high time of the output clock signal and adjusts the bias signal in response thereto.

3. The duty cycle correction device of claim 1 , wherein the pulse generator comprises:

a delay element that generates an inverted, delayed input clock signal based on the input clock signal; and

circuitry that generates the reset signal based on the input clock signal and the inverted, delayed input clock signal.

4. The duty cycle correction device of claim 1 , wherein the voltage controlled delay element comprises:

a first inverter that generates an inverted, delayed reset signal based on the reset signal;

circuitry responsive to the bias signal; and

a second inverter that generates the modified reset signal based on the inverted, delayed reset signal and the circuitry.

5. The duty cycle correction device of claim 1 , wherein the voltage controlled delay element further comprises:

a plurality of voltage controlled delay elements that generate a plurality of modified reset signals based on the reset signal and the bias signal; and

a multiplexer that generates the modified reset signal based on the plurality of modified reset signals and a select signal.

6. The duty cycle correction device of claim 1 , wherein the flip-flop comprises:

an asynchronous resettable flip-flop that generates the output clock signal based on the input clock signal and the modified reset signal.

7. A method for generating an output clock signal with a desired duty cycle based on an input clock signal comprising:

inputting the input clock signal to a pulse generator;

generating a reset signal from the pulse generator based on the input clock signal;

inputting the reset signal and a bias signal to a voltage controlled delay element;

generating a modified reset signal from the voltage controlled delay element;

generating the output clock signal from a flip-flop, wherein the input clock signal and the modified reset signal serve as an inputs to the flip-flop;

inputting the output clock signal to a duty cycle controller; and

generating the bias signal from the duty cycle controller.

8. The method of claim 7 , wherein generating the bias signal comprises:

monitoring a high time of the output clock signal and adjusting the bias signal in response thereto.

9. The method of claim 7 , wherein generating the reset signal using the pulse generator comprises:

generating an inverted, delayed input clock signal using a delay element dependent on the input clock signal; and

generating the reset signal using circuitry dependent on the input clock signal and the inverted, delayed clock signal.

10. The method of claim 7 , wherein generating the modified reset signal using the voltage controlled delay element comprises:

generating an inverted, delayed reset signal from a first inverter dependent on the reset signal; and

generating a modified reset signal from a second inverter dependent on the inverted, delayed reset signal and circuitry dependent on the bias signal.

11. The method of claim 7 , wherein the generating the modified reset signal comprises:

inputting the reset signal and the bias signal to a plurality of voltage controlled delay elements;

generating a plurality of modified reset signals using the plurality of voltage controlled delay elements;

inputting the plurality of modified reset signals and select signals to a multiplexer; and

generating the modified reset signal using the multiplexer.

12. The method of claim 7 , wherein the generating the output clock signal using the flip-flop comprises:

inputting the input clock signal and the modified reset signal to a resettable flip-flop; and

generating the output clock signal from the resettable flip-flop.

13. An apparatus for generating an output clock signal with a desired duty cycle dependent on an input clock signal, comprising:

means for generating a reset signal based on the input clock signal;

means for generating a modified reset signal based on the reset signal and a bias signal, wherein a delay of the means for generating is controlled by the bias signal;

a flip-flop for generating the output clock signal, wherein the input clock signal and the modified reset signal serve as an inputs to the flip-flop; and

means for generating the bias signal based on the output clock signal.

14. An apparatus for generating an output clock signal with a desired duty cycle dependent on an input clock signal, comprising:

a pulse generator having an input operatively connected to the input clock signal, wherein the pulse generator outputs a reset signal in response thereto;

a voltage controlled delay element having an input operatively connected to an output of the pulse generator, wherein the voltage controlled delay element outputs a modified reset signal in response to a bias signal and the reset signal;

a flip-flop having an input operatively connected to the input clock signal, wherein the flip-flop outputs the output clock signal in response to the modified reset signal and the input clock signal, wherein the modified reset signal and the input clock signal serve as inputs to the flip-flop; and

a duty cycle controller having an input operatively connected to an output of the flip-flop, wherein the duty cycle controller outputs the bias signal in response to the output clock signal.

15. The apparatus of claim 14 , wherein the output of the duty cycle controller is operatively connected to a capacitance.