IP Library Granted Patent US 6,990,612
Granted Patent B2
US 6,990,612 · App. 10/198,868 · Granted Jan 24, 2006

System and method for preventing software errors

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Quick Facts
Patent No.
US 6,990,612
App. No.
10/198,868
Granted
Jan 24, 2006
Kind
B2
Abstract

The present invention provides systems and methods for preventing software errors caused by address range or alignment errors. In architecture, a representative system includes a compiler that parses a program and further comprises a logic that generates a verification value for a block of code in the program, a logic that stores the verification value in the block of code, and a logic that inserts verification value instruction code into the block of code. The present invention can also be viewed as a method for preventing software errors in a program. A representative method operates by generating a verification value for a block of code in the program, and storing the verification value in the block of code. During execution of the program, a runtime verification value is generated for the block of code, and the block of code is executed if the verification value equals the runtime verification value, and generates an error message if the verification value does not equals the runtime verification value.

Claims (51)

1. A method for preventing software errors in a program, said method comprising steps of:

generating a verification value for a block of code in the program, the block of code corresponding to one of a statically allocated object, a procedure call and a function call;

storing the verification value in the block of code;

computing a runtime verification value for the block of code during execution of the program;

executing the block of code if the verification value equals the runtime verification value; and

generating an error message if the verification value does not equal the runtime verification value.

2. The method of claim 1 , wherein the generating a verification value step further comprises:

allocating area for the generated verification value.

3. The method of claim 1 , wherein the generating a verification value step further comprises:

inserting the verification value in the block of code.

4. The method of claim 1 , further comprising the step of:

inserting verification value instruction code into the block of code.

5. The method of claim 1 , wherein the generating a verification value step further comprises:

using a parameter to generate the verification value, wherein the parameter is selected from the group consisting of a base address of the block of code, number of elements in the block of code, type of the elements in the block of code, and order of the elements in the block of code.

6. The method of claim 1 , wherein the verification value is a hash value.

7. The method of claim 1 , wherein the steps of generating a verification value, storing, computing, executing and generating an error message are performed for each block of code corresponding to a statically allocated object, a procedure call or a function call.

8. A system for preventing software errors in a program, comprising:

means for generating a verification value for a block of code in the program, the block of code corresponding to one of a statically allocated object, a procedure call and a function call;

means for storing the verification value in the block of code; and

means for computing a runtime verification value for the block of code during execution of the program, wherein the computing means executes the block of code if the verification value equals the runtime verification value, and generates an error message if the verification value does not equal the runtime verification value.

9. The system of claim 8 , wherein the generating means further comprises:

means for allocating area for the generated verification value.

10. The system of claim 8 , wherein the generating means further comprises:

means for inserting the verification value in the block of code.

11. The system of claim 8 , wherein the generating means further comprises:

means for inserting verification value instruction code into the block of code.

12. The system of claim 8 , wherein the verification value is generated using a parameter, wherein the parameter is selected from the group consisting of a base address of the block of code, number of elements in the block of code, type of the elements in the block of code, and order of the elements in the block of code.

13. The system of claim 8 , wherein the verification value is a hash value.

14. A computer readable medium stored on a computer readable memory and executing on a computer for preventing software errors in a program, comprising:

logic for generating a verification value for a block of code in the program, the block of code corresponding to one of a statically allocated object, a procedure call and a function call;

logic for storing the verification value in the block of code; and

logic for computing a runtime verification value for the block of code during execution of the program, wherein the computing logic executes the block of code if the verification value equals the runtime verification value, and generates an error message if the verification value does not equal the runtime verification value.

15. The computer readable medium of claim 14 , wherein said logic for generating a verification value further comprises:

logic for allocating area for the verification value.

16. The computer readable medium of claim 14 , wherein said logic for generating a verification value further comprises:

logic for inserting the verification value in the block of code.

17. The computer readable medium of claim 14 , wherein said logic for generating a verification value further comprises:

logic for inserting verification value instruction code into the block of code.

18. The computer readable medium of claim 14 , wherein the verification value is generated using a parameter, wherein the parameter is selected from the group consisting of a base address of the block of code, number of elements in the block of code, type of the elements in the block of code, and order of the elements in the block of code.

19. The computer readable medium of claim 14 , wherein the verification value is a hash value.

20. A system with computer readable medium stored on a computer readable memory and executing on a computer for preventing software errors in a program, comprising:

a compiler that parses a program, wherein the compiler further comprises:

logic that generates a verification value for a block of code in the program, the block of code corresponding to one of a statically allocated object, a procedure call and a function call;

logic that stores the verification value in the block of code; and

logic that inserts verification value instruction code into the block of code.

21. The system of claim 20 , wherein the compiler further comprises:

logic that allocates area in the block of code for the verification value.

22. The system of claim 20 , wherein the compiler further comprises:

logic that for inserts the verification value in the block of code.

23. The system of claim 20 , wherein the verification value is generated using a parameter, wherein the parameter is selected from the group consisting of a base address of the block of code, number of elements in the block of code, type of the elements in the block of code, and order of the elements in the block of code.

24. The system of claim 20 , wherein the verification value is a hash value.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2021
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 056157/0492 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2003
From: HEWLETT-PACKARD COMPANY
To: HEWLETT-PACKARD DEVELOPMENT COMPANY L.P.
Reel/Frame 014061/0492 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2003
From: HEWLETT-PACKARD COMPANY
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 013776/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2003
From: DWYER, LAWRENCE D.K.B.
To: HEWLETT-PACKARD COMPANY
Reel/Frame 013685/0881 →