Algorithm mapping, specialized instructions and architecture features for smart memory computing
View Patent ↗A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.
1. A smart memory integrated circuit comprises:
an instruction memory;
a plurality of data memory blocks that store data for general storage;
a plurality of multi-port register files coupled to said data memory blocks to provide storage of temporary data;
an input cross-bar switch coupled to said register files;
a plurality of execution units coupled to said input cross-bar switch and thus to said register files and said data memory blocks, said execution units execute instructions stored in said instruction memory; and
an output cross-bar switch coupled from said execution units to said register files,
wherein said instruction memory supplies the same instruction to said execution units operating concurrently.
2. A smart memory integrated circuit as recited in claim 1 , wherein said smart memory integrated circuit further comprises:
a plurality of Local Execution Registers (LERs), each of the LERs being associated with one of said execution units to locally store and supply control and data therefor.
3. A smart memory integrated circuit as recited in claim 2 , wherein said smart memory integrated circuit further comprises:
a Global Execution Register (GER) to globally store and supply control and data to each of said execution units.
4. A smart memory integrated circuit as recited in claim 3 , wherein said smart memory integrated circuit further comprises:
execution control logic operatively connected to said execution units, said LERs and said GER, said execution control logic operates to validate or invalidate use of data from said GER or said LERs.
5. A smart memory integrated circuit as recited in claim 4 , wherein said smart memory integrated circuit further comprises:
a plurality of control and status registers;
control logic;
a plurality of configuration registers; and
bus interface logic.
6. A smart memory integrated circuit as recited in claim 3 , wherein said GER comprises:
a coefficient register;
a mask register; and
a pass register.
7. A smart memory integrated circuit as recited in claim 2 , wherein each of said LERs comprise:
a data point register;
a data attribute register; and
a predicate register.
8. A smart memory integrated circuit as recited in claim 2 , wherein said smart memory integrated circuit further comprises:
execution control logic operatively connected to said execution units, said LERs and said GER, said execution control logic operates to validate or invalidate use of data from said GER or said LERs.
9. A smart memory integrated circuit as recited in claim 8 , wherein said smart memory integrated circuit further comprises:
a plurality of control and status registers;
control logic;
a plurality of configuration registers; and
bus interface logic.
10. A smart memory integrated circuit as recited in claim 1 , wherein the number of said data memory blocks exceeds the number of said execution units.
11. A smart memory integrated circuit as recited in claim 10 , wherein the number of said data memory blocks is n, where n is an integer, and wherein the number of said execution units is n−2.
12. A smart memory integrated circuit as recited in claim 1 ,
wherein said smart memory integrated circuit further comprises a plurality of register files coupled to said output cross-bar switch to receive outputs from said execution units, and
wherein said data memory blocks couple to said input crossbar switch via said register files.
13. A smart memory integrated circuit as recited in claim 12 , wherein the number of said data memory blocks exceeds the number of said execution units, and wherein the number of said register files exceeds the number of said execution units.
14. A smart memory integrated circuit as recited in claim 12 , wherein the number of said data memory blocks is n, where n is an integer, wherein the number of said register files is n, and wherein the number of said execution units is n−2.
15. A smart memory integrated circuit as recited in claim 12 , wherein said smart memory integrated circuit further comprises:
a plurality of Local Execution Registers (LERs), each of the LERs being associated with one of said execution units to locally store and supply control and data therefor.
16. A smart memory integrated circuit as recited in claim 15 , wherein said smart memory integrated circuit further comprises:
a Global Execution Register (GER) to globally store and supply control and data to each of said execution units.
17. A smart memory integrated circuit as recited in claim 16 , wherein said smart memory integrated circuit further comprises:
execution control logic operatively connected to said execution units, said LERs and said GER, said execution control logic operates to validate or invalidate use of data from said GER or said LERs.
18. A smart memory integrated circuit as recited in claim 1 , wherein said smart memory integrated circuit is a monolithic integrated circuit.
19. A smart memory integrated circuit as recited in claim 1 , wherein said execution units can load data from any of said register files through said input cross-bar switch, process the data, and then store data to any said register files through said output cross-bar switch.
20. A smart memory integrated circuit as recited in claim 1 , wherein said execution units execute the same instruction code at the same time from said instruction memory to index said register files related to the index of said execution unit.
21. A smart memory integrated circuit as recited in claim 1 , wherein the number of said data memory blocks or said register files is larger than the number of said execution units.
22. A smart memory integrated circuit as recited in claim 1 , wherein said smart memory integrated circuit further comprises:
a Global Execution Register (GER) and a plurality of Local Execution Registers (LERs) such that each of said execution unit is operatively connected to said GER and one of said LERs so that each of said execution units can be parameterized while executing the same instruction code from said instruction memory.
23. A smart memory integrated circuit as recited in claim 1 , wherein data stored in said data memory blocks are organized as an object mapped directly from data points in a program with high data-level parallelism.
24. A smart memory integrated circuit as recited in claim 23 , wherein the mapping from the data points in the program to data in said data memory blocks preserves the physical location of the data points.
25. A smart memory integrated circuit as recited in claim 23 , wherein the object comprises old, current, and next data, parameters, and attributes information to process one iteration.