A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6 , and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3 . Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
1. A single chip microprocessor comprising:
a first processing unit including an instruction register and an instruction decoder;
a second processing unit;
first, second and third address buses coupled to the first processing unit;
first, second and third data buses;
a first memory coupled to the first and second address buses and to the first and second data buses; and
a second memory coupled to the first and third address buses and to the first and third data buses;
wherein the instruction decoder decodes an instruction fetched in the instruction register and provides control signals to the second processing unit according to the decoding of the instruction.
2. The single chip microprocessor of claim 1 , wherein the second processing unit includes a decoding unit decoding the control signals.
3. The single chip microprocessor claim 1 , wherein the first processing unit comprises a CPU and the second processing unit comprises a DSP.
4. The single chip microprocessor of claim 1 , wherein the first processing unit comprises a RISC CPU and the second processing unit comprises DSP.
5. The single chip microprocessor of claim 1 , wherein the instruction decoder decodes instructions of a first bit length and a second bit length, wherein the second bit length is greater than the first bit length.
6. The single chip microprocessor of claim 5 , wherein the first processing unit operates responsive to the decoding of instructions of the first bit length, and the second processing unit operates responsive to the decoding of instructions of the second bit length.
7. The single chip microprocessor of claim 6 , wherein the second processing unit also operates responsive to the decoding of instructions of the first bit length.
8. The single chip microprocessor of claim 5 , wherein the second bit length is an integer multiple of the first bit length.
9. The single chip microprocessor of claim 8 , wherein the second bit length equals 32 and the first bit length equals 16.