AlGaAs or InGaP low turn-on voltage GaAs-based heterojunction bipolar transistor
View Patent ↗A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer allow the heterojunction bipolar transistor to realize a lower turn-on voltage threshold. The thickness of the emitter layer if utilized is kept to a minimum to reduce the associated space charge recombination current in the heterojunction bipolar transistor.
1. A compound semiconductor device, comprising:
a first GaAs layer:
a second GaAs layer formed on the first GaAs layer;
a third p-type GaAs layer formed on the second GaAs layer;
a p-type In y Ga 1−y As layer (0.0≦Y≦0.3) formed on the third GaAs layer;
an n type In x Ga 1−x P layer (0.5<x<0.7) formed on the In y Ga 1−y As layer;
an n type In 0.51 Ga 0.49 P layer formed on the n type In x Ga 1−x P layer;
an n type GaAs layer formed on the n type In 0.51 Ga 0.49 P layer; and
an n type In x Ga 1−x As layer (0.0<x<0.6) formed on the n type GaAs layer.
2. A compound semiconductor device, comprising:
a first GaAs layer:
a second GaAs layer formed on the first GaAs layer;
a third p-type GaAs layer formed on the second GaAs layer;
a p-type In y Ga 1−y As layer (0.0≦y≦0.3) formed on the third GaAs layer;
an n type In y Al x Ga 1−x ) 1−y As layer (0.0<y<0.15) (0.0<x<0.3) formed on the In y Ga 1−y As layer;
an n type Al 0.3 Ga 0.7 As layer formed on the n type In y (Al x Ga 1−x ) 1−y As layer;
an n type Al x Ga 1−x As (0.0<x <0.3) layer formed on the n type Al 0.3 Ga 0.7 As layer;
an n type GaAs layer formed on the n type Al x Ga 1−x As layer; and
an n type In x Ga 1−x As layer (0.0<x<0.6) formed on the n type GaAs layer.
3. A compound semiconductor device, comprising:
a first GaAs layer:
a second GaAs layer formed on the first GaAs layer;
a p-type GaAs layer formed on the second GaAs layer;
an p-type GaAs 1−x Sb x layer (0.0≦x≦0.3) formed on the third GaAs layer;
an n type In y (Al x Ga 1−x ) 1−y As layer (0.0<y<0.3) (0.0<x<0.3) formed on the GaAs 1−x Sb x layer;
an n type Al 0.3 Ga 0.7 As layer formed on the n type In y (Al x Ga 1−x ) 1−y As layer;
an n type Al x Ga 1−x As (0.0<x<0.5) layer formed on the n type Al 0.3 Ga 0.7 As layer;
an n type GaAs layer formed on the n type Al x Ga 1−x As layer; and
an n type In x Ga 1−x As layer (0.0<x<0.6) formed on the n type GaAs layer.
4. A heterojunction bipolar transistor, comprising,
a contact having at least one layer of a first material;
an emitter having an emitter spacer of an n type In x Ga 1−x P (0.5<x<0.7) material;
a base having a base spacer of an GaAs 1−x Sb x (0.0≦x≦0.3) material; and
a collector having at least one layer of said first material.