Method for manufacturing mask ROM
View Patent ↗A method for manufacturing a mask ROM of flat cell structure. The method includes the steps of: providing a semiconductor substrate having a flat cell array region and a peripheral circuit region; forming a first and a second mask patterns exposing a substrate portions corresponding to a diffusion layer formation region of the flat cell array region and a device isolation layer of the peripheral circuit region; ion-implanting an impurity in the exposed substrate portions; forming a trench by etching the exposed substrate portion peripheral circuit region; forming a linear oxide layer on the first and the second mask patterns and the surface of the trench, a diffusion layer on the flat cell array region, and a barrier oxide layer on the surface of diffusion layer in accordance with a thermal oxidation process; depositing an oxide layer on the linear oxide layer to fill up the trench; polishing the oxide layer to expose the surface of the first and the second mask patterns; and forming a diffusion layer on the flat cell array region and a trench type isolation layer on the peripheral circuit region by removing the first and the second mask patterns.
1. A method for manufacturing a mask ROM of flat cell structure comprising the steps of:
providing a semiconductor substrate having a flat cell array region and a peripheral circuit region;
forming a first and a second mask patterns exposing the substrate portions corresponding to a diffusion layer formation region of the flat cell array region and a device isolation layer of the peripheral circuit region;
ion-implanting an impurity in the exposed substrate portions;
forming a trench by etching the exposed substrate portion of the peripheral circuit region;
forming a linear oxide layer on the first and the second mask patterns and the surface of the trench, a diffusion layer on the flat cell array region, and a barrier oxide layer on the surface of diffusion layer in accordance with a thermal oxidation process;
depositing an oxide layer on the linear oxide layer to fill up the trench;
polishing the oxide layer to expose the surface of the first and second mask patterns; and
forming a diffusion layer on the flat cell array region and a trench type isolation layer on the peripheral circuit region by removing the fist and the second mask patters.
2. The method for manufacturing a mask ROM of flat cell structure according to claim 1 , wherein the first and the second mask patterns have a structure of multi-layered film comprising two or more layers.
3. The method for manufacturing a mask ROM of flat cell structure according to claim 2 , wherein the first and the second mask patterns have structure of multi-layered film comprising a first insulating layer, a buffer layer and a second insulating layer.
4. The method for manufacturing a mask ROM of flat cell structure according to claim 1 , wherein after the step of forming the first and the second mask patterns and before the stop of ion-implanting an impurity, further comprising a step of masking the peripheral circuit region so that the impurity ion implantation has a depth not deeper than that of the trench.
5. The method for manufacturing a mask ROM of flat cell structure according to claim 1 , wherein the step of forming a trench is carried out after masking the flat cell array region.
6. The method for manufacturing a mask ROM of flat cell structure according to claim 1 , wherein, the step of ion-implanting an impurity, conductive impurities opposite to the substrate are ion-implanted in high concentration.
7. The method for manufacturing a mask ROM of flat cell structure according to claim 1 , wherein the itinerary oxide layer has a thickness of 50˜400 Å.
8. The method for manufacturing a mask ROM of flat cell structure according to claim 1 , wherein, after the step of forming the first and the second mask patterns and before the step of ion-implanting an impurity, further comprising a stop of forming a spacer on sidewalls of the first and the second mask patterns.