Methods and apparatus for multi-processing execution of computer instructions
View Patent ↗A multi-processing computer architecture and a method of operating the same are provided. The multi-processing architecture provides a main processor and multiple sub-processors cascaded together to efficiently execute loop operations. The main processor executes operations outside of a loop and controls the loop. The multiple sub-processors are operably interconnected, and are each assigned by the main processor to a given loop iteration. Each sub-processor is operable to receive one or more sub-instructions sequentially, operate on each sub-instruction and propagate the sub-instruction to a subsequent sub-processor.
1. A multi-processing computer system, comprising:
a main processor operable to manage processing of instruction loops of a program, each instruction loop including one or more sub-instructions; and
a plurality of sub-processors operable to process each sub-instruction in a plurality of sequential stages, at least a first one of the sub-processors being operable to sequentially receive the one or more sub-instructions from the main processor and to propagate the sub-instruction to a subsequent one of the sub-processors, and at least a second one of the sub-processors being operable to sequentially receive the one or more sub-instructions from the first sub-processor;
wherein the main processor and the plurality of sub-processors are cascaded together.
2. The multi-processing computer system according to claim 1 , wherein each sub-processor operates on a given one of the sub-instructions with a respective instruction processing pipeline.
3. The multi-processing computer system according to claim 2 , wherein the instruction processing pipeline for each sub-processor operates sequentially during one or more cycles.
4. The multi-processing computer system according to claim 3 , wherein an instruction decoding is performed during a first cycle, an address calculation is performed during a second cycle and an instruction execution is performed during a third cycle.
5. The multi-processing computer system according to claim 4 , wherein a write back operation is performed during a fourth cycle.
6. The multi-processing computer system according to claim 1 , wherein the plurality of sub-processors do not accept interrupts.
7. The multi-processing computer system according to claim 1 , wherein the plurality of sub-processors are operably connected to electronic memory.
8. The multi-processing computer system according to claim 7 , wherein the plurality of sub-processors access the electronic memory directly.
9. The multi-processing computer system according to claim 1 , wherein the main processor is operably connected to electronic memory.
10. The multi-processing computer system according to claim 9 , wherein the electronic memory is a cache memory.
11. The multi-processing computer system according to claim 1 , wherein the main processor forms part of a first device and at least some of the plurality of sub-processors form part of a second device, the second device being remote from and cascaded with the first device.
12. The multi-processing computer system according to claim 1 , wherein the main processor is operable to detect an event for the one or more sub-processors, and upon detecting the event, the main processor sequentially outputs the one or more sub-instructions to the first one of the sub-processors.
13. The multi-processing computer system according to claim 12 , wherein the main processor detects the event prior to initiating one or more of the instruction loops, and the main processor controls operation of the plurality of sub-processors.
14. The multi-processing computer system according to claim 1 , wherein the main processor is capable of executing general computer instructions.
15. The multi-processing computer system according to claim 1 , wherein the main processor is capable of accepting interrupts.
16. The multi-processing computer system according to claim 1 , wherein the main processor employs a parallel architecture.
17. The multi-processing computer system according to claim 16 , wherein the parallel architecture is a super-scalar architecture.
18. The multi-processing computer system according to claim 16 , wherein the parallel architecture is a very long instruction word architecture (VLIW).
19. The multi-processing computer system according to claim 1 , wherein the main processor includes an ALU and a register file, and the ALU and the register file are operable to treat vector data.
20. The multi-processing computer system according to claim 1 , wherein the main processor identifies how many sub-processors are available.
21. The multi-processing computer system according to claim 20 , wherein the main processor identifies a number of loop sets and a number of remainder loops to perform.
22. The multi-processing computer system according to claim 21 , wherein, if the number of loop sets is greater than zero, then the main processor sets a loop counter equal to the plurality of sub-processors that are available, sequentially sends the one or more sub-instructions to the first one of the sub-processors along with the loop counter, and decrements the number of loop sets after all of the sub-instructions in a given instruction loop are passed to the first one of the sub-processors.
23. The multi-processing computer system according to claim 21 , wherein, if the number of loop sets is equal to zero and the number of remainder loops is greater than zero, then the main processor sets a loop counter equal to the number of remainder loops and sequentially sends the one or more sub-instructions to the first one of the sub-processors along with the loop counter.
24. The multi-processing computer system according to claim 1 , wherein a given sub-processor from among the plurality of sub-processors decrements a loop counter upon receiving a new sub-instruction, and if the loop counter is greater than zero, the given sub-processor passes the new sub-instruction to a next one of the plurality of sub-processors along with the loop counter, and if the loop counter is zero, the given sub-processor does not pass the new sub-instruction to the next one of the sub-processors.
25. A multi-processing computer system, comprising:
a main processor operable to manage processing of instruction loops of a program, each instruction loop including one or more sub-instructions;
a plurality of sub-processors operable to process each sub-instruction in a plurality of sequential stages, the main processor and the plurality of sub-processors being cascaded together, at least a first one of the sub-processors being operable to sequentially receive the one or more sub-instructions from the main processor and to propagate the sub-instruction to a subsequent one of the sub-processors, and at least a second one of the sub-processors being operable to sequentially receive the one or more sub-instructions from the first sub-processor; and
a cascading bus operable to provide the one or more sub-instructions from the main processor to the first one of the sub-processors.
26. The multi-processing computer system according to claim 25 , wherein the cascading bus is bi-directional.
27. The multi-processing computer system according to claim 26 , wherein the cascading bus provides loop data from the main processor to the first one of the sub-processors, the loop data including one or more of instruction code, decoded information, shading data, parameters and a loop counter.
28. The multi-processing computer system according to claim 26 , wherein the cascading bus provides one or more of status information and result information from one or more of the plurality of sub-processors to the main processor.
29. The multi-processing computer system according to claim 25 , further including an additional processor device cascaded to the main processor.
30. The multi-processing computer system according to claim 29 , wherein the additional processor device includes an additional main processor.
31. The multi-processing computer system according to claim 30 , wherein the additional main processor operates as one of the plurality of sub-processors.
32. The multi-processing computer system according to claim 31 , wherein the additional main processor is selected to operate as one of the plurality of sub-processors by a mode select mechanism.
33. A multi-processing method, comprising:
managing processing of instruction loops of a program with a main processor, each instruction loop including one or more sub-instructions;
sequentially receiving the one or more sub-instructions from the main processor in a first sub-processor, the first sub-processor being one of a plurality of sub-processors, the main processor and the plurality of sub-processors being cascaded together;
processing each sub-instruction in a plurality of sequential stages;
propagating the one or more sub-instructions to a subsequent one of the sub-processors if not all of the instruction loops have been completed; and
sequentially receiving the one or more sub-instructions in a second one of the sub-processors,
so that execution of the instruction loops is obtained using the plurality of sub-processors.
34. The multi-processing method according to claim 33 , wherein processing in the plurality of sequential stages includes the first sub-processor operating on given ones of the sub-instructions with an instruction processing pipeline.
35. The multi-processing method according to claim 34 , further including sequentially operating the instruction processing pipeline during one or more cycles.
36. The multi-processing method according to claim 35 , further including:
performing instruction decoding on a first sub-instruction in a first cycle;
performing address calculation on the first sub-instruction in a second cycle; and
performing instruction execution on the first sub-instruction in a third cycle.
37. The multi-processing method according to claim 36 , further including performing a write back operation on the first sub-instruction in a fourth cycle.
38. The multi-processing method according to claim 35 , further including, when a given instruction loop includes a first sub-instruction and a second sub-instruction:
performing instruction decoding on the first sub-instruction in a first cycle;
performing address calculation on the first sub-instruction in a second cycle;
performing instruction decoding on the second sub-instruction in the second cycle;
performing instruction execution on the first sub-instruction in a third cycle;
performing address calculation on the second sub-instruction in the third cycle; and
performing instruction execution on the second sub-instruction in a fourth cycle.
39. The multi-processing method according to claim 38 , further including:
performing a write back operation on the first sub-instruction in the fourth cycle; and
performing the write back operation on the second sub-instruction in a fifth cycle.
40. The multi-processing method according to claim 33 , further including:
prior to sequentially receiving the one or more sub-instructions, detecting an event at the main processor; and
sequentially outputting the one or more sub-instructions to the first sub-processor.
41. The multi-processing method according to claim 33 , wherein, when the main processor includes an instruction fetch mechanism, retrieving the instruction loops from an instruction memory cache using the instruction fetch mechanism.
42. The multi-processing method according to claim 33 , further including:
determining a number of sub-processors available;
identifying a number of loop sets to perform; and
identifying a number of remainder loops to perform.
43. The multi-processing method according to claim 42 , further including, if the number of loop sets is greater than zero:
setting a loop counter equal to the plurality of sub-processors that are available;
propagating the one or more sub-instructions to the subsequent one of the sub-processors along with the loop counter; and
decrementing the number of loop sets after all of the sub-instructions in a given instruction loop are propagated to the first sub-processor.
44. The multi-processing method according to claim 42 , further including, if the number of loop sets is equal to zero and the number of remainder loops is greater than zero:
setting a loop counter equal to the number of remainder loops; and
propagating the one or more sub-instructions to the subsequent one of the sub-processors along with the loop counter.
45. A multi-processing method, comprising:
selecting an active main processor from among a first main processor and a second main processor, the first main processor being located in a first device and the second main processor being located in a second device;
managing processing of instruction loops of a program with the active main processor, each instruction loop including one or more sub-instructions;
sequentially receiving the one or more sub-instructions from the active main processor in a first sub-processor, the first sub-processor being one of a plurality of sub-processors, the active main processor and the plurality of sub-processors being cascaded together;
processing each sub-instruction in a plurality of sequential stages;
propagating the one or more sub-instructions to a subsequent one of the sub-processors if a loop counter is greater than zero; and
sequentially receiving the one or more sub-instructions in a second one of the sub-processors,
so that execution of the instruction loops is obtained using the plurality of sub-processors.
46. The multi-processing method according to claim 45 , wherein selecting the active main processor is performed using a mode select mechanism.
47. The multi-processing method according to claim 45 , wherein the first main processor is selected as the active main processor and the second main processor operates as one of the plurality of sub-processors.
48. The multi-processing computer system according to claim 1 , wherein instructions for execution by the main processor are distinguishable from the sub-instructions for the sub-processors.
49. The multi-processing computer system according to claim 48 , wherein discriminating instructions identify the starting and ending points for the sub-instructions.
50. The multi-processing computer system according to claim 48 , wherein the instruction for execution by the main processor and the sub-instructions for the sub-processors are distinguished by instruction operation codes.
51. The multi-processing method according to claim 33 , further comprising distinguishing instructions for execution by the main processor from the sub-instructions for the sub-processors.
52. The multi-processing computer system according to claim 51 , wherein the sub-instructions for the sub-processors are distinguished from the main processor instructions by defining macro instructions for the sub-instructions and calling one or more of the sub-instructions when a given macro instruction is executed.