Array substrate for liquid crystal display device and fabricating method thereof
View Patent ↗An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, the gate line connected to a gate pad, a data line on the substrate, the data line connected to a data pad and crossing the gate line for defining a pixel region, a thin film transistor connected to the gate line and the data line, the thin film having a gate electrode and source and drain electrodes, a passivation layer having a first contact hole exposing the drain electrode, a second contact hole exposing the gate pad, and a third contact hole exposing the data pad, a black matrix on the passivation layer, a first conductive pattern covering the first contact hole, a pixel electrode on the passivation layer at the pixel region, the pixel electrode contacting the first conductive pattern, an auxiliary gate pad connected to the gate pad through the second contact hole, and an auxiliary data pad connected to the data pad through the third contact hole.
1. An array substrate for a liquid crystal display device, comprising:
a substrate;
a gate line on the substrate, the gate line connected to a gate pad;
a data line on the substrate, the data line connected to a data pad and crossing the gate line for defining a pixel region;
a thin film transistor connected to the gate line and the data line, the thin film transistor having a gate electrode and source and drain electrodes;
a passivation layer over the gate line, the data line, and the thin film transistor, the passivation layer having a first contact hole exposing the drain electrode, a second contact hole exposing the gate pad, and a third contact hole exposing the data pad;
a black matrix on the passivation layer over the thin film transistor;
a first conductive pattern covering the first contact hole, wherein the first conductive pattern is formed of the same material as the black matrix, and wherein the first conductive pattern is formed in the same layer as the black matrix;
a pixel electrode on a surface of the passivation layer at the pixel region, the pixel electrode contacting the first conductive pattern;
an auxiliary gate pad connected to the gate pad through the second contact hole; and
an auxiliary data pad connected to the data pad through the third contact hole.
2. The substrate according to claim 1 , wherein the gate line and the data line are formed of one of aluminum, aluminum alloy, copper, and copper alloy.
3. The substrate according to claim 1 , wherein the pixel electrode is formed of one of indium-tin-oxide and indium-zinc-oxide.
4. The substrate according to claim 1 , wherein the black matrix is formed of one of chromium, molybdenum, and titanium.
5. The substrate according to claim 1 , further comprising a second conductive pattern interposed between the gate pad and the auxiliary gate pad.
6. The substrate according to claim 5 , wherein the second conductive pattern is formed of the same material as the black matrix.
7. The substrate according to claim 1 , further comprising a third conductive pattern interposed between the data pad and the auxiliary data pad.
8. The substrate according to claim 7 , wherein the third conductive pattern is formed of the same material as the black matrix.
9. The substrate according to claim 5 , further comprising a third conductive pattern interposed between the data pad and the auxiliary data pad.
10. The substrate according to claim 9 , wherein the third conductive pattern is formed of the same material as the black matrix.
11. The substrate according to claim 1 , wherein at least a portion of the black matrix is covered with the pixel electrode.
12. The substrate according to claim 11 , wherein the black matrix is fully covered with the pixel electrode.
13. The substrate according to claim 1 , wherein the auxiliary gate pad is formed of the same material as the pixel electrode.
14. The substrate according to claim 1 , wherein the auxiliary data pad is formed of the same material as the pixel electrode.
15. A fabricating method of an array substrate for a liquid crystal display device, comprising:
forming a gate line on a substrate to connect to a gate pad;
forming a data line on the substrate to connect to a data pad and to cross the gate line to define a pixel region;
forming a thin film transistor connected to the gate line and the data line, the thin film transistor having a gate electrode and source and drain electrodes;
forming a passivation layer over the gate line, the data line, and the thin film transistor, the passivation layer having a first contact hole exposing the drain electrode, a second contact hole exposing the gate pad, and a third contact hole exposing the data pad;
simultaneously forming a black matrix and a first conductive pattern on the passivation layer, wherein the black matrix is formed over the thin film transistor, and the first conductive pattern covers the first contact hole; and
simultaneously forming a pixel electrode, an auxiliary gate pad and an auxiliary data pad on a surface of the passivation layer, wherein the pixel electrode contacts the first conductive pattern at the pixel region, the auxiliary gate pad is connected to the gate pad through the second contact hole, and the auxiliary data pad is connected to the data pad through the third contact hole.
16. The method according to claim 15 , wherein the gate line and the data line is formed of one of aluminum, aluminum alloy, copper, and copper alloy.
17. The method according to claim 15 , wherein the pixel electrode is formed of one of indium-tin-oxide and indium-zinc-oxide.
18. The method according to claim 15 , wherein the black matrix is formed of one of chromium, molybdenum, and titanium.
19. The method according to claim 15 , wherein a second conductive pattern is simultaneously formed with the black matrix and the first conduct pattern between the gate pad and the auxiliary gate pad.
20. The method according to claim 15 , wherein a third conductive pattern is simultaneously formed with the black matrix and the first conductive pattern between the data pad and the auxiliary data pad.