Space time block coded transmit antenna diversity for WCDMA
View Patent ↗A circuit comprising a channel encoder circuit coupled to receive an input data sequence and produce an output data sequence. An interleaver circuit coupled to receive the output data sequence and produce an interleaved data sequence. An encoder circuit coupled to receive the interleaved sequence and produce a first encoded symbol at a first output terminal at a first time and produce a first transform of a second encoded symbol at a second output terminal at the first time and produce the second encoded symbol at the first output terminal at a second time and produce a second transform of the first encoded symbol at the second output terminal at the second time.
1. A circuit, comprising:
a first output terminal;
a second output terminal;
a channel encoder circuit coupled to receive an input data sequence and produce an output data sequence;
an interleaver circuit coupled to receive the output data sequence and produce an interleaved data sequence; and
an encoder circuit coupled to receive the interleaved sequence and produce a first encoded symbol at the first output terminal at a first dine and produce a first transform of a second encoded symbol at the second output terminal at the first time and produce the second encoded symbol at the first output terminal at a second time and produce a second transform of the first encoded symbol at the second output terminal at the second time.
2. A circuit as in claim 1 , wherein the input data sequence comprises a sequence of data bits.
3. A circuit as in claim 2 , wherein the output data sequence comprises a sequence of encoded data bits.
4. A circuit as in claim 3 , wherein the sequence of encoded data bits is greater in number than the sequence of input data bits.
5. A circuit as in claim 1 , wherein the output data sequence is encoded with a convolutional code.
6. A circuit as in claim 1 , wherein the output data sequence is encoded with a turbo code.
7. A circuit as in claim 1 , wherein the interleaved data sequence comprises data bits of the output data sequence having a different order than the output data sequence.
8. A circuit as in claim 1 , wherein each of the encoded symbols is a quadrature phase shift keyed symbol.
9. A circuit as in claim 8 , wherein said quadrature phase shift keyed symbol comprises an inphase data bit and a quadrature data bit from the interleaved data sequence.
10. A circuit as in claim 1 , wherein each of the encoded symbols is multiplied by a channel orthogonalization code.
11. A circuit as in claim 10 , wherein the channel orthogonalization code comprises a long code and a Walsh code.
12. A circuit as in claim 11 , wherein the Walsh code corresponds to a remote receiver.
13. A circuit as in claim 1 , wherein the first output terminal is coupled to a first antenna and the second output terminal is coupled to a second antenna.
14. A circuit as in claim 13 , wherein one of the first and second transforms is a conjugate.
15. A circuit as in claim 13 , wherein one of the first and second transforms is a negative of a conjugate.