IP Library Granted Patent US 7,860,375
Granted Patent B2
US 7,860,375 · App. 10/204,729 · Granted Dec 28, 2010

Method and apparatus for simultaneous recording and displaying two different video programs

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,860,375
App. No.
10/204,729
Granted
Dec 28, 2010
Kind
B2
Abstract

A method and apparatus for simultaneously recording and displaying video signals from two different video sources. The apparatus comprises a main channel processing circuit, a second channel processing circuit, and common circuitry. The common circuit comprises a digital video decoder pipe that decodes both first and second encoded video signals. A PIP picture is produced using a common reference clock that is derived from the first video signal. In a record mode, a second channel clock reference is coupled to the second channel processing circuit to produce a recordable signal using a digital encoder. The recordable signal also forms a PIP picture that is coupled to the main channel processing circuit to produce a PIP picture that is used to monitor the recording process.

Claims (20)

1. A method of simultaneously recording and viewing a plurality of video signals comprising the steps of:

(a) decoding, using a first clock reference signal, a first video signal from a first video source in a common shared video decoder pipe;

(b) decoding, using said first clock reference signal, a second video signal from a second video source in the common shared video decoder pipe when said first and second video signals are to be displayed as a main picture and a picture in picture (PIP) picture;

c) encoding, using a second clock reference signal, said second video signal when said first video signal is to be displayed and said second video signal is to be recorded.

2. The method of claim 1 wherein said step (c) further comprises displaying said second video signal while recording said second video signal, as a PIP picture.

3. The method of claim 1 wherein said video decoder pipe decodes moving pictures expert group (MPEG) encoded video signals.

4. The method of claim 1 wherein the second clock reference signal is derived from the first clock reference signal.

5. The method of claim 1 , wherein said first video signal and said second video signal have different decoding rates and a clock of one of said first video signal and said second a video signal having the faster decode rate is used as the first clock reference signal.

6. Apparatus for simultaneously recording and displaying a plurality of video signals comprising:

a common shared video decoder pipe for decoding said plurality of video signals from different video sources using a first clock reference signal;

a main channel processing circuit, coupled to said common shared video decoder pipe, for producing a main picture from a first of said plurality of video signals for display;

a second channel processing circuit, coupled to said common shared video decoder pipe, for producing a decoded video signal from a second of said plurality of video signals for PIP display and for encoding said second of said plurality of video signals using a second clock reference signal for recording.

7. The apparatus of claim 6 further comprising:

a reference clock generator coupled to said main channel processing circuit and said second channel processing circuit; and

a channel clock generator coupled to said second channel processing circuit.

8. The apparatus of claim 7 wherein said second channel clock generator derives a channel clock signal from a reference clock signal generated by said reference clock generator.

9. The apparatus of claim 6 wherein said second channel processing circuit comprises a digital encoder for producing an analog signal for recording.

10. The apparatus of claim 9 wherein said digital encoder produces an internal vertical synchronization signal.

11. The apparatus of claim 6 , wherein said apparatus is contained within a video receiver.

12. The apparatus of claim 6 , wherein said apparatus is contained within a video processing device.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2018
From: THOMSON LICENSING DTV
To: INTERDIGITAL MADISON PATENT HOLDINGS
Reel/Frame 046763/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2017
From: THOMSON LICENSING
To: THOMSON LICENSING DTV
Reel/Frame 043302/0965 →
CHANGE OF NAME Recorded Apr 21, 2017
From: THOMSON LICENSING S.A.
To: THOMSON LICENSING
Reel/Frame 042303/0268 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2002
From: CARLSGAARD, ERIC STEPHEN; HORLANDER, THOMAS EDWARD
To: THOMSON LICENSING S.A.
Reel/Frame 013797/0814 →